541 lines
16 KiB
C
541 lines
16 KiB
C
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/*
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* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!
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* @file imx_i2c.c
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* @brief Main driver for the I2C controller. It initializes the controller
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* and handles the master mode.
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*
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* @ingroup diag_i2c
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*/
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#include "sdk.h"
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#include "imx_i2c.h"
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#include "imx_i2c_internal.h"
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#include "registers/regsi2c.h"
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#include "ccm_pll.h"
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#include "interrupt.h"
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//! Set this macro to 1 to enable tracing of data send and receive.
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#define TRACE_I2C 0
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//! @brief Get the irq id of I2C by instance number.
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//! @param x I2C instance number, from 1 through 3.
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#define I2C_IRQS(x) ( (x) == HW_I2C1 ? IMX_INT_I2C1 : (x) == HW_I2C2 ? IMX_INT_I2C2 : (x) == HW_I2C3 ? IMX_INT_I2C3 : 0xFFFFFFFF)
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////////////////////////////////////////////////////////////////////////////////
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// Constants
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////////////////////////////////////////////////////////////////////////////////
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static const uint16_t i2c_freq_div[50][2] = {
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{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
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{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
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{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
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{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
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{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
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{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
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{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
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{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
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{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
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{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
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{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
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{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
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{ 3072, 0x1E }, { 3840, 0x1F }
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};
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////////////////////////////////////////////////////////////////////////////////
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// Prototypes
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////////////////////////////////////////////////////////////////////////////////
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static inline int is_bus_free(unsigned int instance);
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static int wait_till_busy(uint32_t instance);
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static inline void imx_send_stop(unsigned int instance);
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static int wait_op_done(uint32_t instance, int is_tx);
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static int tx_byte(uint8_t * data, uint32_t instance);
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static int rx_bytes(uint8_t * data, uint32_t instance, int sz);
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static void set_i2c_clock(uint32_t instance, uint32_t baud);
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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unsigned i2c_get_request_instance(const imx_i2c_request_t * rq)
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{
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// First see if there device info is set.
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if (rq->device)
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{
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// Use the instance number in the device info.
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return rq->device->port;
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}
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// Check if the ctl_addr is within the range of instances.
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if (rq->ctl_addr >= 1 && rq->ctl_addr <= HW_I2C_INSTANCE_COUNT)
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{
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// Valid instance number, so use it directly.
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return rq->ctl_addr;
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}
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else
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{
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// Not a valid instance, so treat it as a base address.
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return REGS_I2C_INSTANCE(rq->ctl_addr);
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}
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}
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/*!
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* @brief Loop status register for IBB to go 0.
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*
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* The loop also breaks on max number of iterations.
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*
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* @param instance Instance number of the I2C module.
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*
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* @return 0 if successful; -1 otherwise
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*/
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static inline int is_bus_free(unsigned int instance)
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{
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int i = WAIT_RXAK_LOOPS;
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while (HW_I2C_I2SR(instance).B.IBB && (--i > 0));
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if (i <= 0) {
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debug_printf("Error: I2C Bus not free!\n");
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return -1;
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}
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return 0;
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}
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/*!
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* @brief Loop status register for IBB to go 1.
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*
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* It breaks the loop if there's an arbitration lost occurred or the maximum
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* number of iterations has been reached.
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*
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* @param instance Instance number of the I2C module.
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*
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* @return 0 if successful; -1 otherwise
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*/
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static int wait_till_busy(uint32_t instance)
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{
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int i = WAIT_BUSY_LOOPS;
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while (!HW_I2C_I2SR(instance).B.IBB && (--i > 0)) {
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if (HW_I2C_I2SR(instance).B.IAL) {
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debug_printf("Error: arbitration lost!\n");
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return -1;
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}
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}
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if (i <= 0) {
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debug_printf("I2C Error: timeout in %s; %d\n", __FUNCTION__, __LINE__);
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return -1;
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}
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return 0;
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}
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/*!
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* Generates a STOP signal, called by rx and tx routines
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*
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* @param instance Instance number of the I2C module.
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*
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* @return none
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*/
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static inline void imx_send_stop(unsigned int instance)
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{
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HW_I2C_I2CR(instance).B.MSTA = 0;
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}
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/*!
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* @brief Wait for operation done.
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*
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* This function loops until we get an interrupt. On timeout it returns -1.
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* It reports arbitration lost if IAL bit of I2SR register is set
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* Clears the interrupt
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* If operation is transfer byte function will make sure we received an ack
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*
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* @param instance Instance number of the I2C module.
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* @param is_tx Pass 1 for transfering, 0 for receiving
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*
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* @return 0 if successful; negative integer otherwise
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*/
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static int wait_op_done(uint32_t instance, int is_tx)
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{
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hw_i2c_i2sr_t v;
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int i = WAIT_RXAK_LOOPS;
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// Loop until we get an interrupt
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do {
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v.U = HW_I2C_I2SR_RD(instance);
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} while (!v.B.IIF && (--i > 0));
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// If timeout error occurred return error
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if (i <= 0) {
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debug_printf("I2C Error: timeout unexpected\n");
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return -1;
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}
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// Clear the interrupts
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HW_I2C_I2SR_WR(instance, 0);
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// Check for arbitration lost
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if (v.B.IAL) {
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debug_printf("Error %d: Arbitration lost\n", __LINE__);
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return ERR_ARB_LOST;
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}
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// Check for ACK received in transmit mode
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if (is_tx) {
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if (v.B.RXAK) {
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// No ACK received, generate STOP by clearing MSTA bit
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debug_printf("Error %d: no ack received\n", __LINE__);
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// Generate a STOP signal
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imx_send_stop(instance);
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return ERR_NO_ACK;
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}
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}
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return 0;
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}
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/*!
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* @brief Implements a loop to send a byte to I2C slave.
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*
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* For master transmit. Always expect a RXAK signal to be set!
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*
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* @param data return buffer for data
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* @param instance Instance number of the I2C module.
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*
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* @return 0 if successful; -1 otherwise
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*/
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static int tx_byte(uint8_t * data, uint32_t instance)
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{
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#if TRACE_I2C
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debug_printf("%s(data=0x%02x, instance=%d)\n", __FUNCTION__, *data, instance);
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#endif // TRACE_I2C
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// clear both IAL and IIF bits
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HW_I2C_I2SR_WR(instance, 0);
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// write to data register
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HW_I2C_I2DR_WR(instance, *data);
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// wait for transfer of byte to complete
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return wait_op_done(instance, 1);
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}
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/*!
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* @brief Implements a loop to receive bytes from I2C slave.
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*
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* For master receive.
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*
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* @param data return buffer for data
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* @param instance Instance number of the I2C module.
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* @param sz number of bytes to receive
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*
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* @return 0 if successful; -1 otherwise
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*/
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static int rx_bytes(uint8_t * data, uint32_t instance, int sz)
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{
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int i;
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for (i = 0; sz > 0; sz--, i++) {
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if (wait_op_done(instance, 0) != 0) {
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return -1;
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}
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// the next two if-statements setup for the next read control register value
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if (sz == 1) {
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// last byte --> generate STOP
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// generate STOP by clearing MSTA bit
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imx_send_stop(instance);
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}
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if (sz == 2) {
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// 2nd last byte --> set TXAK bit to NOT generate ACK
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HW_I2C_I2CR(instance).B.TXAK = 1;
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}
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// read the true data
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data[i] = HW_I2C_I2DR_RD(instance);
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#if TRACE_I2C
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debug_printf("OK 0x%02x\n", data[i]);
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#endif // TRACE_I2C
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}
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return 0;
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}
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static void set_i2c_clock(uint32_t instance, uint32_t baud)
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{
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// Adjust the divider to get the closest SCL frequency to baud rate
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uint32_t src_clk = get_main_clock(IPG_PER_CLK);
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uint32_t divider = src_clk / baud;
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uint8_t index = 0;
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if (divider < i2c_freq_div[0][0])
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{
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divider = i2c_freq_div[0][0];
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index = 0;
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debug_printf("Warning :can't find a smaller divider than %d.\n", divider);
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debug_printf("SCL frequency is set at %d - expected was %d.\n", src_clk/divider, baud);
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}
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else if (divider > i2c_freq_div[49][0])
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{
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divider = i2c_freq_div[49][0];
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index = 49;
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debug_printf("Warning: can't find a bigger divider than %d.\n", divider);
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debug_printf("SCL frequency is set at %d - expected was %d.\n", src_clk/divider, baud);
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}
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else
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{
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for (index = 0; i2c_freq_div[index][0] < divider; index++);
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divider = i2c_freq_div[index][0];
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}
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HW_I2C_IFDR_WR(instance, BF_I2C_IFDR_IC(i2c_freq_div[index][1]));
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}
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int i2c_xfer(const imx_i2c_request_t *rq, int dir)
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{
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uint32_t reg;
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uint32_t ret = 0;
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uint16_t i2cr;
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uint8_t i;
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uint8_t data;
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uint32_t instance = i2c_get_request_instance(rq);
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uint8_t address = (rq->device ? rq->device->address : rq->dev_addr) << 1;
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if (rq->buffer_sz == 0 || rq->buffer == NULL) {
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debug_printf("Invalid register address size=%x, buffer size=%x, buffer=%x\n",
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rq->reg_addr_sz, rq->buffer_sz, (unsigned int)rq->buffer);
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return ERR_INVALID_REQUEST;
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}
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// clear the status register
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HW_I2C_I2SR_WR(instance, 0);
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// enable the I2C controller
|
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HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN);
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// Check if bus is free, if not return error
|
||
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if (is_bus_free(instance) != 0) {
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return -1;
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||
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}
|
||
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|
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// If the request has device info attached and it has a non-zero bit rate, then
|
||
|
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// change the clock to the specified rate.
|
||
|
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if (rq->device && rq->device->freq)
|
||
|
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{
|
||
|
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set_i2c_clock(instance, rq->device->freq);
|
||
|
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}
|
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|
|
// Step 1: Select master mode, assert START signal and also indicate TX mode
|
||
|
|
HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN | BM_I2C_I2CR_MSTA | BM_I2C_I2CR_MTX);
|
||
|
|
|
||
|
|
// make sure bus is busy after the START signal
|
||
|
|
if (wait_till_busy(instance) != 0) {
|
||
|
|
debug_printf("1\n");
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
// Step 2: send slave address + read/write at the LSB
|
||
|
|
data = address | I2C_WRITE;
|
||
|
|
|
||
|
|
if ((ret = tx_byte(&data, instance)) != 0) {
|
||
|
|
debug_printf("START TX ERR %d\n", ret);
|
||
|
|
|
||
|
|
if (ret == ERR_NO_ACK) {
|
||
|
|
return ERR_NO_ACK_ON_START;
|
||
|
|
} else {
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Step 3: send I2C device register address
|
||
|
|
if (rq->reg_addr_sz > 4) {
|
||
|
|
debug_printf("Warning register address size %d should less than 4\n", rq->reg_addr_sz);
|
||
|
|
return ERR_INVALID_REQUEST;
|
||
|
|
}
|
||
|
|
|
||
|
|
reg = rq->reg_addr;
|
||
|
|
|
||
|
|
for (i = 0; i < rq->reg_addr_sz; i++, reg >>= 8) {
|
||
|
|
data = reg & 0xFF;
|
||
|
|
|
||
|
|
#if TRACE_I2C
|
||
|
|
debug_printf("sending I2C=%d device register: data=0x%x, byte %d\n", instance, data, i);
|
||
|
|
#endif // TRACE_I2C
|
||
|
|
|
||
|
|
if (tx_byte(&data, instance) != 0) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Step 4: read/write data
|
||
|
|
if (dir == I2C_READ) {
|
||
|
|
// do repeat-start
|
||
|
|
HW_I2C_I2CR(instance).B.RSTA = 1;
|
||
|
|
|
||
|
|
// make sure bus is busy after the REPEATED START signal
|
||
|
|
if (wait_till_busy(instance) != 0) {
|
||
|
|
return ERR_TX;
|
||
|
|
}
|
||
|
|
|
||
|
|
// send slave address again, but indicate read operation
|
||
|
|
data = address | I2C_READ;
|
||
|
|
|
||
|
|
if (tx_byte(&data, instance) != 0) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
// change to receive mode
|
||
|
|
i2cr = HW_I2C_I2CR_RD(instance) & ~BM_I2C_I2CR_MTX;
|
||
|
|
|
||
|
|
// if only one byte to read, make sure don't send ack
|
||
|
|
if (rq->buffer_sz == 1) {
|
||
|
|
i2cr |= BM_I2C_I2CR_TXAK;
|
||
|
|
}
|
||
|
|
HW_I2C_I2CR_WR(instance, i2cr);
|
||
|
|
|
||
|
|
// dummy read
|
||
|
|
data = HW_I2C_I2DR_RD(instance);
|
||
|
|
|
||
|
|
// now reading ...
|
||
|
|
if (rx_bytes(rq->buffer, instance, rq->buffer_sz) != 0) {
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
// I2C_WRITE
|
||
|
|
for (i = 0; i < rq->buffer_sz; i++) {
|
||
|
|
// send device register value
|
||
|
|
data = rq->buffer[i];
|
||
|
|
|
||
|
|
if ((ret = tx_byte(&data, instance)) != 0) {
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
// generate STOP by clearing MSTA bit
|
||
|
|
imx_send_stop(instance);
|
||
|
|
|
||
|
|
// Check if bus is free, if not return error
|
||
|
|
if (is_bus_free(instance) != 0) {
|
||
|
|
debug_printf("WARNING: bus is not free\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
// disable the controller
|
||
|
|
HW_I2C_I2CR_WR(instance, 0);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
int i2c_read(const imx_i2c_request_t *rq)
|
||
|
|
{
|
||
|
|
return i2c_xfer(rq, I2C_READ);
|
||
|
|
}
|
||
|
|
|
||
|
|
int i2c_write(const imx_i2c_request_t *rq)
|
||
|
|
{
|
||
|
|
return i2c_xfer(rq, I2C_WRITE);
|
||
|
|
}
|
||
|
|
|
||
|
|
void i2c_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool state)
|
||
|
|
{
|
||
|
|
uint32_t irq_id = I2C_IRQS(instance);
|
||
|
|
|
||
|
|
if (state) {
|
||
|
|
// register the IRQ sub-routine
|
||
|
|
register_interrupt_routine(irq_id, irq_subroutine);
|
||
|
|
|
||
|
|
// enable the IRQ at the ARM core level
|
||
|
|
enable_interrupt(irq_id, CPU_0, 0);
|
||
|
|
|
||
|
|
// clear the status register
|
||
|
|
HW_I2C_I2SR_WR(instance, 0);
|
||
|
|
|
||
|
|
// and enable the interrupts in the I2C controller
|
||
|
|
HW_I2C_I2CR(instance).B.IIEN = 1;
|
||
|
|
} else {
|
||
|
|
// disable the IRQ at the ARM core level
|
||
|
|
disable_interrupt(irq_id, CPU_0);
|
||
|
|
|
||
|
|
// and disable the interrupts in the I2C controller
|
||
|
|
HW_I2C_I2CR(instance).B.IIEN = 0;
|
||
|
|
|
||
|
|
// clear the status register
|
||
|
|
HW_I2C_I2SR_WR(instance, 0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int i2c_init(uint32_t base, uint32_t baud)
|
||
|
|
{
|
||
|
|
int instance;
|
||
|
|
|
||
|
|
// Accept either an instance or base address for the base param.
|
||
|
|
if (base >= 1 && base <= HW_I2C_INSTANCE_COUNT)
|
||
|
|
{
|
||
|
|
instance = base;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
instance = REGS_I2C_INSTANCE(base);
|
||
|
|
}
|
||
|
|
|
||
|
|
// enable the source clocks to the I2C port
|
||
|
|
clock_gating_config(REGS_I2C_BASE(instance), CLOCK_ON);
|
||
|
|
|
||
|
|
// Set iomux configuration
|
||
|
|
i2c_iomux_config(instance);
|
||
|
|
|
||
|
|
// reset I2C
|
||
|
|
HW_I2C_I2CR_WR(instance, 0);
|
||
|
|
|
||
|
|
// Set clock.
|
||
|
|
set_i2c_clock(instance, baud);
|
||
|
|
|
||
|
|
// set an I2C slave address
|
||
|
|
HW_I2C_IADR_WR(instance, IMX6_DEFAULT_SLAVE_ID);
|
||
|
|
|
||
|
|
// clear the status register
|
||
|
|
HW_I2C_I2SR_WR(instance, 0);
|
||
|
|
|
||
|
|
// enable the I2C controller
|
||
|
|
HW_I2C_I2CR_WR(instance, BM_I2C_I2CR_IEN);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|
||
|
|
// EOF
|
||
|
|
////////////////////////////////////////////////////////////////////////////////
|