140 lines
2.9 KiB
C
140 lines
2.9 KiB
C
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/*
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* Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-02-09 CDT first version
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*/
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#include <board.h>
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#include <drv_wktm.h>
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#if defined(RT_USING_PM)
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#if defined(BSP_USING_PM)
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// #define DRV_DEBUG
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#define LOG_TAG "drv_wktm"
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#include <drv_log.h>
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#define CMPVAL_MAX (0xFFFUL)
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#if defined(BSP_USING_WKTM_XTAL32)
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#define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_XTAL32)
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#define PWC_WKT_COUNT_FRQ (32768UL)
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#elif defined(BSP_USING_WKTM_64HZ)
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#define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_64HZ)
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#define PWC_WKT_COUNT_FRQ (64U)
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#else
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#if defined(HC32F4A0)
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#define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_RTCLRC)
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#elif defined(HC32F460)
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#define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_LRC)
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#endif
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#define PWC_WKT_COUNT_FRQ (32768UL)
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#endif
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static rt_uint32_t cmpval = CMPVAL_MAX;
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/**
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* This function get current count value of WKTM
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* @param None
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* @return the count value
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*/
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rt_uint32_t hc32_wktm_get_current_tick(void)
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{
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return (CMPVAL_MAX);
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}
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/**
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* This function get the max value that WKTM can count
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* @param None
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* @return the max count
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*/
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rt_uint32_t hc32_wktm_get_tick_max(void)
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{
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return (CMPVAL_MAX);
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}
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/**
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* This function start WKTM with reload value
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* @param reload The value that Comparison value of the Counter
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* @return RT_EOK
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*/
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rt_err_t hc32_wktm_start(rt_uint32_t reload)
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{
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/* 64HZ must use XTAL32 and run RTC */
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#if defined(BSP_USING_WKTM_64HZ)
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#if defined(BSP_RTC_USING_XTAL32)
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if (DISABLE == RTC_GetCounterState())
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{
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/* #error "Please start the RTC!" */
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RT_ASSERT(0);
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}
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#else
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#error "Please enable XTAL32 and start the RTC!"
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#endif
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#endif
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if (reload > CMPVAL_MAX || !reload)
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{
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return -RT_ERROR;
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}
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cmpval = reload;
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PWC_WKT_SetCompareValue(cmpval);
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PWC_WKT_Cmd(ENABLE);
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return RT_EOK;
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}
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/**
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* @brief This function stop WKTM
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* @param None
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* @retval None
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*/
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void hc32_wktm_stop(void)
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{
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PWC_WKT_Cmd(DISABLE);
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}
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/**
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* This function get the count clock of WKTM
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* @param None
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* @return the count clock frequency in Hz
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*/
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rt_uint32_t hc32_wktm_get_countfreq(void)
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{
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return PWC_WKT_COUNT_FRQ;
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}
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/**
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* @brief This function initialize the wktm
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* @param None
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* @retval type code
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*/
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int rt_hw_wktm_init(void)
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{
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rt_err_t ret = RT_EOK;
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/* Disable WKTM in advance */
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PWC_WKT_Cmd(DISABLE);
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/* WKTM init */
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PWC_WKT_Config(PWC_WKT_CLK_SRC, CMPVAL_MAX);
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#if defined(HC32F4A0)
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/* F4A0 if select RTCLRC clock need open the LRCEN by RTC->CR3 register */
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#if (PWC_WKT_CLK_SRC == PWC_WKT_CLK_SRC_RTCLRC)
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MODIFY_REG8(CM_RTC->CR3, RTC_CR3_LRCEN, 0x01U << RTC_CR3_LRCEN_POS);
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#endif
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#endif
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return ret;
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}
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INIT_DEVICE_EXPORT(rt_hw_wktm_init);
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#endif
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#endif /* RT_USING_PM */
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