2013-01-08 22:40:58 +08:00
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/* RT-Thread config file */
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#ifndef __RTTHREAD_CFG_H__
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#define __RTTHREAD_CFG_H__
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/* RT_NAME_MAX*/
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#define RT_NAME_MAX 8
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/* RT_ALIGN_SIZE*/
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#define RT_ALIGN_SIZE 4
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/* PRIORITY_MAX*/
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#define RT_THREAD_PRIORITY_MAX 32
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#define IDLE_THREAD_STACK_SIZE 1024
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/* Tick per Second*/
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#define RT_TICK_PER_SECOND 100
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/* CPU Frequency 200MHz */
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#define RT_CPU_FREQ 200
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/* SECTION: RT_DEBUG */
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/* open debug for system assert */
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// #define RT_DEBUG
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/* Thread Debug*/
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/* #define RT_THREAD_DEBUG */
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/* #define RT_SCHEDULER_DEBUG */
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/* Using Hook*/
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#define RT_USING_HOOK
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/* SECTION: IPC */
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/* Using Semaphore*/
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#define RT_USING_SEMAPHORE
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/* Using Mutex*/
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#define RT_USING_MUTEX
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/* Using Event*/
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#define RT_USING_EVENT
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/* Using MailBox*/
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#define RT_USING_MAILBOX
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/* Using Message Queue*/
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#define RT_USING_MESSAGEQUEUE
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/* SECTION: Memory Management */
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/* Using Memory Pool Management*/
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#define RT_USING_MEMPOOL
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/* Using Dynamic Heap Management*/
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#define RT_USING_HEAP
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/* Using Small MM*/
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#define RT_USING_SMALL_MEM
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#define RT_TINY_SIZE
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/* SECTION: Device System */
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/* Using Device System*/
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#define RT_USING_DEVICE
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#define RT_USING_UART1
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#define RT_UART_RX_BUFFER_SIZE 64
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/* SECTION: Console options */
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#define RT_USING_CONSOLE
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/* the buffer size of console*/
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#define RT_CONSOLEBUF_SIZE 128
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/* SECTION: FinSH shell options */
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/* Using FinSH as Shell*/
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#define RT_USING_FINSH
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/* Using symbol table */
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#define FINSH_USING_SYMTAB
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#define FINSH_USING_DESCRIPTION
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/* SECTION: lwip, a lighwight TCP/IP protocol stack */
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/* #define RT_USING_LWIP */
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/* Enable ICMP protocol*/
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#define RT_LWIP_ICMP
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/* Enable UDP protocol*/
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#define RT_LWIP_UDP
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/* Enable TCP protocol*/
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#define RT_LWIP_TCP
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/* Enable DNS */
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#define RT_LWIP_DNS
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/* the number of simulatenously active TCP connections*/
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#define RT_LWIP_TCP_PCB_NUM 5
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/* ip address of target*/
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#define RT_LWIP_IPADDR0 192
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#define RT_LWIP_IPADDR1 168
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#define RT_LWIP_IPADDR2 1
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#define RT_LWIP_IPADDR3 30
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/* gateway address of target*/
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#define RT_LWIP_GWADDR0 192
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#define RT_LWIP_GWADDR1 168
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#define RT_LWIP_GWADDR2 1
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#define RT_LWIP_GWADDR3 1
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/* mask address of target*/
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#define RT_LWIP_MSKADDR0 255
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#define RT_LWIP_MSKADDR1 255
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#define RT_LWIP_MSKADDR2 255
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#define RT_LWIP_MSKADDR3 0
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/* tcp thread options */
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#define RT_LWIP_TCPTHREAD_PRIORITY 12
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#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
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#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
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/* ethernet if thread options */
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#define RT_LWIP_ETHTHREAD_PRIORITY 15
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
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#define RT_LWIP_ETHTHREAD_STACKSIZE 512
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#endif
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