2022-11-10 22:22:48 +08:00
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fspim_g.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 09:07:55
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2023-05-11 10:25:21 +08:00
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* Description: This file is for providing spim basic information.
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2022-11-10 22:22:48 +08:00
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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2023-05-11 10:25:21 +08:00
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* 1.0 zhugengyu 2021/12/3 init commit
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* 1.1 zhugengyu 2022/4/15 support test mode
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2022-11-10 22:22:48 +08:00
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*/
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/***************************** Include Files *********************************/
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#include "ftypes.h"
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#include "fparameters.h"
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#include "sdkconfig.h"
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#include "fspim.h"
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#include "fspim_hw.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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const FSpimConfig FSPIM_CONFIG_TBL[FSPI_NUM] =
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{
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[FSPI0_ID] =
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{
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.instance_id = FSPI0_ID, /* Id of device*/
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.base_addr = FSPI0_BASE_ADDR,
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.irq_num = FSPI0_IRQ_NUM,
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.irq_prority = 0,
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.work_mode = FSPIM_DEV_MASTER_MODE,
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.slave_dev_id = FSPIM_SLAVE_DEV_0,
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.max_freq_hz = 4000000,
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.n_bytes = 1,
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.en_test = FALSE,
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.en_dma = FALSE
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},
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[FSPI1_ID] =
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{
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.instance_id = FSPI1_ID, /* Id of device*/
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.base_addr = FSPI1_BASE_ADDR,
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.irq_num = FSPI1_IRQ_NUM,
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.irq_prority = 0,
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.work_mode = FSPIM_DEV_MASTER_MODE,
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.slave_dev_id = FSPIM_SLAVE_DEV_0,
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.max_freq_hz = 4000000,
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.n_bytes = 1,
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.en_test = FALSE,
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.en_dma = FALSE
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},
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#if defined(CONFIG_TARGET_E2000)
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[FSPI2_ID] =
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{
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.instance_id = FSPI2_ID, /* Id of device*/
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.base_addr = FSPI2_BASE,
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.irq_num = FSPI2_IRQ_NUM,
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.irq_prority = 0,
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.work_mode = FSPIM_DEV_MASTER_MODE,
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.slave_dev_id = FSPIM_SLAVE_DEV_0,
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.max_freq_hz = 4000000,
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.n_bytes = 1,
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.en_test = FALSE,
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.en_dma = FALSE
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},
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[FSPI3_ID] =
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{
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.instance_id = FSPI3_ID, /* Id of device*/
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.base_addr = FSPI3_BASE,
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.irq_num = FSPI3_IRQ_NUM,
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.irq_prority = 0,
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.work_mode = FSPIM_DEV_MASTER_MODE,
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.slave_dev_id = FSPIM_SLAVE_DEV_0,
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.max_freq_hz = 4000000,
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.n_bytes = 1,
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.en_test = FALSE,
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.en_dma = FALSE
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},
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#endif
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};
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/*****************************************************************************/
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