347 lines
7.4 KiB
C
347 lines
7.4 KiB
C
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fparameters.h
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-17 17:58:51
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* Description: This file is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#ifndef BSP_BOARD_D2000_PARAMETERS_H
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#define BSP_BOARD_D2000_PARAMETERS_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#if !defined(__ASSEMBLER__)
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#include "ftypes.h"
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#endif
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#define CORE0_AFF 0x0
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#define CORE1_AFF 0x1
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#define CORE2_AFF 0x100
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#define CORE3_AFF 0x101
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#define CORE4_AFF 0x200
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#define CORE5_AFF 0x201
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#define CORE6_AFF 0x300
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#define CORE7_AFF 0x301
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/* cache */
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#define CACHE_LINE_ADDR_MASK 0x3F
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#define CACHE_LINE 64U
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/* Device register address */
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#define FDEV_BASE_ADDR 0x28000000
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#define FDEV_END_ADDR 0x2FFFFFFF
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/* Generic Timer */
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#define GENERIC_TIMER_NS_IRQ_NUM 30
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/* PCI */
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#define FPCIE_NUM 1
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#define FPCIE0_ID 0
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#define FPCIE0_MISC_IRQ_NUM 59
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#define FPCIE_CFG_MAX_NUM_OF_BUS 256
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#define FPCIE_CFG_MAX_NUM_OF_DEV 32
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#define FPCIE_CFG_MAX_NUM_OF_FUN 8
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#define FPCI_CONFIG_BASE_ADDR 0x40000000
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#define FPCI_CONFIG_REG_LENGTH 0x10000000
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#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000
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#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000
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#define FPCI_MEM32_BASE_ADDR 0x58000000
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#define FPCI_MEM32_REG_LENGTH 0x27ffffff
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#define FPCI_MEM64_BASE_ADDR 0x1000000000
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#define FPCI_MEM64_REG_LENGTH 0x1000000000
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#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29900000
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#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29910000
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#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29920000
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#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29930000
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#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29940000
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#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29950000
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#define FPCI_EU0_CONFIG_BASE_ADDR 0x29900000
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#define FPCI_EU1_CONFIG_BASE_ADDR 0x299A0000
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#define FPCI_INTA_IRQ_NUM 60
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#define FPCI_INTB_IRQ_NUM 61
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#define FPCI_INTC_IRQ_NUM 62
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#define FPCI_INTD_IRQ_NUM 63
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#define FPCI_NEED_SKIP 0
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#define FPCI_INTX_EOI
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#define FPCI_INTX_PEU0_STAT 0x29100000
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#define FPCI_INTX_PEU1_STAT 0x29101000
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#define FPCI_INTX_EU0_C0_CONTROL 0x29000184
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#define FPCI_INTX_EU0_C1_CONTROL 0x29010184
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#define FPCI_INTX_EU0_C2_CONTROL 0x29020184
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#define FPCI_INTX_EU1_C0_CONTROL 0x29030184
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#define FPCI_INTX_EU1_C1_CONTROL 0x29040184
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#define FPCI_INTX_EU1_C2_CONTROL 0x29050184
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#define FPCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
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#define FPCI_INTX_SATA_NUM 2 /* Total number of controllers */
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/* platform ahci host */
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#define PLAT_AHCI_HOST_MAX_COUNT 5
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#define AHCI_BASE_0 0
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#define AHCI_BASE_1 0
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#define AHCI_BASE_2 0
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#define AHCI_BASE_3 0
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#define AHCI_BASE_4 0
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#define AHCI_IRQ_0 0
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#define AHCI_IRQ_1 0
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#define AHCI_IRQ_2 0
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#define AHCI_IRQ_3 0
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#define AHCI_IRQ_4 0
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/* UART */
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#if !defined(__ASSEMBLER__)
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enum
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{
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FUART0_ID = 0,
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FUART1_ID,
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FUART2_ID,
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FUART3_ID,
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FUART_NUM
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};
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#endif
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#define FUART0_IRQ_NUM 38
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#define FUART0_BASE_ADDR 0x28000000
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#define FUART0_CLK_FREQ_HZ 48000000
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#define FUART1_IRQ_NUM 39
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#define FUART1_BASE_ADDR 0x28001000
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#define FUART1_CLK_FREQ_HZ 48000000
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#define FUART2_IRQ_NUM 40
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#define FUART2_BASE_ADDR 0x28002000
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#define FUART2_CLK_FREQ_HZ 48000000
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#define FUART3_IRQ_NUM 41
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#define FUART3_BASE_ADDR 0x28003000
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#define FUART3_CLK_FREQ_HZ 48000000
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#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
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#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
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/* QSPI */
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#if !defined(__ASSEMBLER__)
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enum
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{
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FQSPI0_ID = 0,
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FQSPI_NUM
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};
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/* FQSPI cs 0_3, chip number */
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enum
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{
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FQSPI_CS_0 = 0,
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FQSPI_CS_1 = 1,
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FQSPI_CS_2 = 2,
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FQSPI_CS_3 = 3,
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FQSPI_CS_NUM
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};
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#endif
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#define FQSPI_BASE_ADDR 0x28014000
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#define FQSPI_MEM_START_ADDR 0x0
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#define FQSPI_MEM_END_ADDR 0x1FFFFFFF
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/* GIC v3 */
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#define ARM_GIC_NR_IRQS 1024
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#define ARM_GIC_IRQ_START 0
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#define FGIC_NUM 1
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#define GICV3_BASE_ADDR 0x29a00000U
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#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0)
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#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x100000U)
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#define GICV3_RD_OFFSET (2U << 16)
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#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
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/*
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* The maximum priority value that can be used in the GIC.
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*/
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#define GICV3_MAX_INTR_PRIO_VAL 240U
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#define GICV3_INTR_PRIO_MASK 0x000000f0U
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#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */
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#define SGI_INT_MAX 16
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#define SPI_START_INT_NUM 32 /* SPI start at ID32 */
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#define PPI_START_INT_NUM 16 /* PPI start at ID16 */
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#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
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/* GPIO */
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#define FGPIO0_BASE_ADDR (0x28004000)
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#define FGPIO1_BASE_ADDR (0x28005000)
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#define FGPIO0_ID 0
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#define FGPIO1_ID 1
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#define FGPIO_NUM 2
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#define FGPIO0_IRQ_NUM (42) /* gpio0 irq number */
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#define FGPIO1_IRQ_NUM (43) /* gpio1 irq number */
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/* IOMUX */
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#define FIOCTRL_REG_BASE_ADDR 0x28180000
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/* SPI */
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#define FSPI0_BASE_ADDR 0x2800c000
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#define FSPI1_BASE_ADDR 0x28013000
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#define FSPI0_ID 0
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#define FSPI1_ID 1
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#define FSPI_CLK_FREQ_HZ 48000000
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#define FSPI_NUM 2
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#define FSPI0_IRQ_NUM 50
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#define FSPI1_IRQ_NUM 51
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/* I2C */
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#if !defined(__ASSEMBLER__)
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enum
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{
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FI2C0_ID = 0,
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FI2C1_ID = 1,
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FI2C2_ID,
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FI2C3_ID,
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FI2C_NUM
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};
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#endif
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#define FI2C0_BASE_ADDR 0x28006000
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#define FI2C1_BASE_ADDR 0x28007000
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#define FI2C2_BASE_ADDR 0x28008000
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#define FI2C3_BASE_ADDR 0x28009000
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#define FI2C0_IRQ_NUM 44
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#define FI2C1_IRQ_NUM 45
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#define FI2C2_IRQ_NUM 46
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#define FI2C3_IRQ_NUM 47
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#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */
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/* WDT */
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#if !defined(__ASSEMBLER__)
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enum
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{
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FWDT0_ID = 0,
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FWDT1_ID = 1,
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FWDT_NUM
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};
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#endif
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#define FWDT0_REFRESH_BASE_ADDR 0x2800a000
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#define FWDT1_REFRESH_BASE_ADDR 0x28016000
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#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000)
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#define FWDT0_IRQ_NUM 48
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#define FWDT1_IRQ_NUM 49
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#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */
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/* SDCI */
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#if !defined(__ASSEMBLER__)
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enum
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{
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FSDMMC0_ID = 0,
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FSDMMC_NUM
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};
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#endif
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#define FSDMMC0_BASE_ADDR 0x28207C00
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#define FSDMMC0_DMA_IRQ_NUM 52
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#define FSDMMC0_CMD_IRQ_NUM 53
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#define FSDMMC0_ERR_IRQ_NUM 54
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#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */
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/* GMAC */
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#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */
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#if !defined(__ASSEMBLER__)
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enum
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{
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FGMAC0_ID = 0,
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FGMAC1_ID,
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FGMAC_NUM
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};
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#endif
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#define FGMAC0_BASE_ADDR 0x2820C000
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#define FGMAC1_BASE_ADDR 0x28210000
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#define FGMAC0_IRQ_NUM 81
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#define FGMAC1_IRQ_NUM 82
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#define FGMAC_DMA_MIN_ALIGN 128
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#define FGMAC_MAX_PACKET_SIZE 1600
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/* rtc base address */
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#define RTC_CONTROL_BASE 0x2800D000
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#define FT_CPUS_NR CORE_NUM
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/* can */
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#define FCAN_CLK_FREQ_HZ 600000000
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#define FCAN_REG_LENGTH 0x1000
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#define FCAN0_BASE_ADDR 0x28207000
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#define FCAN1_BASE_ADDR 0x28207400
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#define FCAN2_BASE_ADDR 0x28207800
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#define FCAN0_IRQ_NUM 119
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#define FCAN1_IRQ_NUM 123
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#define FCAN2_IRQNUM 124
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#if !defined(__ASSEMBLER__)
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enum
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{
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FCAN0_ID = 0,
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FCAN1_ID = 1,
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FCAN2_ID = 2,
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FCAN_NUM
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};
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif // !
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