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rt-thread/libcpu/mips/common/entry_gcc.S

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[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
add ls2k bsp
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#include <rtconfig.h>
#include "asm.h"
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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#include <rtconfig.h>
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _rtthread_entry
_rtthread_entry:
#ifndef RT_USING_SELF_BOOT
.globl _start
_start:
#endif
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PTR_LA ra, _rtthread_entry
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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/* disable interrupt */
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MTC0 zero, CP0_CAUSE
MTC0 zero, CP0_STATUS # Set CPU to disable interrupt.
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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ehb
add ls2k bsp
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#ifdef ARCH_MIPS64
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dli t0, ST0_KX
MTC0 t0, CP0_STATUS
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#endif
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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/* setup stack pointer */
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PTR_LA sp, _system_stack
PTR_LA gp, _gp
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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[asm] 解决tab和空格混用的问题
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bal rt_cpu_early_init
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop
/* clear bss */
[asm] 解决tab和空格混用的问题
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PTR_LA t0, __bss_start
PTR_LA t1, __bss_end
add ls2k bsp
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[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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_clr_bss_loop:
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sw zero, 0(t0)
bne t1, t0, _clr_bss_loop
addu t0, 4
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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/* jump to RT-Thread RTOS */
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jal rtthread_startup
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop
/* restart, never die */
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j _start
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop