2018-12-24 17:17:27 +08:00
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/*
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* Copyright (c) 2006-2018, Synwit Technology Co.,Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-05-31 ZYH first version
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* 2018-12-10 Zohar_Lee format file
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2021-09-30 17:55:16 +08:00
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* 2020-07-10 lik rewrite
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2018-12-24 17:17:27 +08:00
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*/
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2021-09-30 17:55:16 +08:00
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#include "drv_sram.h"
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2018-12-24 17:17:27 +08:00
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2021-09-30 17:55:16 +08:00
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#ifdef BSP_USING_EXT_SRAM
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2018-12-24 17:17:27 +08:00
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2021-09-30 17:55:16 +08:00
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#define DRV_DEBUG
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#define LOG_TAG "drv.ext_sram"
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#include <drv_log.h>
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2018-12-24 17:17:27 +08:00
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2021-09-30 17:55:16 +08:00
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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static struct rt_memheap system_heap;
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#endif
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2018-12-24 17:17:27 +08:00
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2021-09-30 17:55:16 +08:00
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static int rt_hw_sram_init(void)
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{
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SRAM_InitStructure SRAM_InitStruct;
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2018-12-24 17:17:27 +08:00
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2021-09-30 17:55:16 +08:00
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PORT->PORTP_SEL0 = 0xAAAAAAAA; //PP0-23 => ADDR0-23
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PORT->PORTP_SEL1 = 0xAAAA;
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2018-12-24 17:17:27 +08:00
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2021-09-30 17:55:16 +08:00
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PORT->PORTM_SEL0 = 0xAAAAAAAA; //PM0-15 => DATA15-0
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PORT->PORTM_INEN = 0xFFFF;
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2018-12-24 17:17:27 +08:00
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2021-09-30 17:55:16 +08:00
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PORT->PORTM_SEL1 = 0xAAA; //PM16 => OEN,PM17 => WEN,PM18 => NORFL_CSN,PM19 => SDRAM_CSN,PM20 => SRAM_CSN,PM21 => SDRAM_CKE
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SRAM_InitStruct.ClkDiv = SRAM_CLKDIV_8;
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SRAM_InitStruct.DataWidth = SRAM_DATAWIDTH_16;
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SRAM_Init(&SRAM_InitStruct);
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#ifdef RT_USING_MEMHEAP_AS_HEAP
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/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
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rt_memheap_init(&system_heap, "sram", (void *)EXT_SRAM_BEGIN, EXT_SRAM_SIZE);
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#endif
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2018-12-24 17:17:27 +08:00
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return 0;
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}
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2021-09-30 17:55:16 +08:00
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INIT_BOARD_EXPORT(rt_hw_sram_init);
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#endif /* BSP_USING_EXT_SRAM */
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