2023-08-29 10:27:54 +08:00
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#ifndef RT_CONFIG_H__
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#define RT_CONFIG_H__
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/* Automatically generated file; DO NOT EDIT. */
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/* RT-Thread Project Configuration */
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/* RT-Thread Kernel */
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#define RT_NAME_MAX 16
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#define RT_CPUS_NR 1
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2023-08-29 10:27:54 +08:00
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#define RT_ALIGN_SIZE 4
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#define RT_THREAD_PRIORITY_32
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#define RT_THREAD_PRIORITY_MAX 32
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#define RT_TICK_PER_SECOND 1000
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#define RT_USING_OVERFLOW_CHECK
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#define RT_USING_HOOK
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#define RT_HOOK_USING_FUNC_PTR
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#define RT_USING_IDLE_HOOK
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#define RT_IDLE_HOOK_LIST_SIZE 4
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#define IDLE_THREAD_STACK_SIZE 8192
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#define RT_USING_TIMER_SOFT
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#define RT_TIMER_THREAD_PRIO 4
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#define RT_TIMER_THREAD_STACK_SIZE 8192
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/* kservice optimization */
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#define RT_KSERVICE_USING_STDLIB
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#define RT_KPRINTF_USING_LONGLONG
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#define RT_USING_DEBUG
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#define RT_DEBUGING_COLOR
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#define RT_DEBUGING_CONTEXT
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/* Inter-Thread communication */
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#define RT_USING_SEMAPHORE
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#define RT_USING_MUTEX
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#define RT_USING_EVENT
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#define RT_USING_MAILBOX
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#define RT_USING_MESSAGEQUEUE
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/* Memory Management */
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#define RT_PAGE_MAX_ORDER 16
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#define RT_USING_SLAB
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#define RT_USING_MEMHEAP
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#define RT_MEMHEAP_FAST_MODE
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#define RT_USING_SLAB_AS_HEAP
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#define RT_USING_HEAP_ISR
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#define RT_USING_HEAP
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#define RT_USING_DEVICE
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#define RT_USING_CONSOLE
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#define RT_CONSOLEBUF_SIZE 128
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#define RT_CONSOLE_DEVICE_NAME "uart1"
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2023-11-21 17:42:23 +08:00
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#define RT_VER_NUM 0x50100
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#define RT_BACKTRACE_LEVEL_MAX_NR 32
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/* AArch64 Architecture Configuration */
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#define ARCH_TEXT_OFFSET 0x80000
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#define ARCH_RAM_OFFSET 0x80000000
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#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
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#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
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2023-11-21 17:42:23 +08:00
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#define ARCH_CPU_64BIT
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#define RT_USING_CACHE
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2023-12-08 17:57:55 +08:00
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#define RT_USING_HW_ATOMIC
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#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
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#define RT_USING_CPU_FFS
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#define ARCH_MM_MMU
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#define ARCH_ARM
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#define ARCH_ARM_MMU
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#define ARCH_ARMV8
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2023-08-29 10:27:54 +08:00
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/* RT-Thread Components */
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#define RT_USING_COMPONENTS_INIT
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#define RT_USING_USER_MAIN
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#define RT_MAIN_THREAD_STACK_SIZE 8192
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#define RT_MAIN_THREAD_PRIORITY 10
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#define RT_USING_MSH
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#define RT_USING_FINSH
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#define FINSH_USING_MSH
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#define FINSH_THREAD_NAME "tshell"
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#define FINSH_THREAD_PRIORITY 20
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#define FINSH_THREAD_STACK_SIZE 4096
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#define FINSH_USING_HISTORY
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#define FINSH_HISTORY_LINES 5
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#define FINSH_USING_SYMTAB
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#define FINSH_CMD_SIZE 80
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#define MSH_USING_BUILT_IN_COMMANDS
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#define FINSH_USING_DESCRIPTION
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#define FINSH_ARG_MAX 10
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#define FINSH_USING_OPTION_COMPLETION
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2023-08-29 10:27:54 +08:00
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/* DFS: device virtual file system */
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#define RT_USING_DFS
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#define DFS_USING_POSIX
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#define DFS_USING_WORKDIR
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#define DFS_FD_MAX 16
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#define RT_USING_DFS_V1
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#define DFS_FILESYSTEMS_MAX 4
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#define DFS_FILESYSTEM_TYPES_MAX 4
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#define RT_USING_DFS_ELMFAT
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/* elm-chan's FatFs, Generic FAT Filesystem Module */
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#define RT_DFS_ELM_CODE_PAGE 437
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#define RT_DFS_ELM_WORD_ACCESS
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#define RT_DFS_ELM_USE_LFN_3
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#define RT_DFS_ELM_USE_LFN 3
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#define RT_DFS_ELM_LFN_UNICODE_0
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#define RT_DFS_ELM_LFN_UNICODE 0
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#define RT_DFS_ELM_MAX_LFN 255
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#define RT_DFS_ELM_DRIVES 2
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#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
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#define RT_DFS_ELM_REENTRANT
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#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
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#define RT_USING_DFS_DEVFS
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#define RT_USING_DFS_RAMFS
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/* Device Drivers */
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#define RT_USING_DEVICE_IPC
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#define RT_UNAMED_PIPE_NUMBER 64
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#define RT_USING_SYSTEM_WORKQUEUE
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#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
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#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
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#define RT_USING_SERIAL
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#define RT_USING_SERIAL_V1
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#define RT_SERIAL_USING_DMA
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#define RT_SERIAL_RB_BUFSZ 64
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#define RT_USING_CAN
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#define RT_CAN_USING_CANFD
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#define RT_USING_I2C
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#define RT_USING_I2C_BITOPS
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#define RT_USING_PIN
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#define RT_USING_NULL
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#define RT_USING_ZERO
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#define RT_USING_RANDOM
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#define RT_USING_PWM
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#define RT_USING_RTC
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#define RT_USING_SDIO
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#define RT_SDIO_STACK_SIZE 8192
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#define RT_SDIO_THREAD_PRIORITY 15
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#define RT_MMCSD_STACK_SIZE 8192
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#define RT_MMCSD_THREAD_PREORITY 22
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#define RT_MMCSD_MAX_PARTITION 16
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#define RT_USING_SPI
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#define RT_USING_QSPI
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#define RT_USING_DEV_BUS
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#define RT_USING_KTIME
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2023-08-29 10:27:54 +08:00
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/* Using USB */
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/* C/C++ and POSIX layer */
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/* ISO-ANSI C layer */
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/* Timezone and Daylight Saving Time */
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#define RT_LIBC_USING_LIGHT_TZ_DST
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#define RT_LIBC_TZ_DEFAULT_HOUR 8
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#define RT_LIBC_TZ_DEFAULT_MIN 0
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#define RT_LIBC_TZ_DEFAULT_SEC 0
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/* POSIX (Portable Operating System Interface) layer */
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#define RT_USING_POSIX_FS
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#define RT_USING_POSIX_DEVIO
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#define RT_USING_POSIX_STDIO
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#define RT_USING_POSIX_TERMIOS
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#define RT_USING_POSIX_DELAY
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#define RT_USING_POSIX_CLOCK
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#define RT_USING_POSIX_TIMER
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/* Interprocess Communication (IPC) */
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/* Socket is in the 'Network' category */
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/* Network */
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2024-01-26 18:31:35 +08:00
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#define RT_USING_SAL
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#define SAL_INTERNET_CHECK
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/* Docking with protocol stacks */
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#define SAL_USING_LWIP
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#define SAL_USING_POSIX
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#define RT_USING_NETDEV
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#define NETDEV_USING_IFCONFIG
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#define NETDEV_USING_PING
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#define NETDEV_USING_NETSTAT
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#define NETDEV_USING_AUTO_DEFAULT
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#define NETDEV_IPV4 1
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#define NETDEV_IPV6 0
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#define RT_USING_LWIP
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#define RT_USING_LWIP212
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#define RT_USING_LWIP_VER_NUM 0x20102
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#define RT_LWIP_MEM_ALIGNMENT 64
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#define RT_LWIP_IGMP
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#define RT_LWIP_ICMP
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#define RT_LWIP_DNS
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/* Static IPv4 Address */
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#define RT_LWIP_IPADDR "192.168.4.10"
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#define RT_LWIP_GWADDR "192.168.4.1"
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#define RT_LWIP_MSKADDR "255.255.255.0"
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#define RT_LWIP_UDP
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#define RT_LWIP_TCP
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#define RT_LWIP_RAW
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#define RT_MEMP_NUM_NETCONN 8
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#define RT_LWIP_PBUF_NUM 512
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#define RT_LWIP_RAW_PCB_NUM 4
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#define RT_LWIP_UDP_PCB_NUM 4
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#define RT_LWIP_TCP_PCB_NUM 4
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#define RT_LWIP_TCP_SEG_NUM 40
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#define RT_LWIP_TCP_SND_BUF 8196
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#define RT_LWIP_TCP_WND 8196
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#define RT_LWIP_TCPTHREAD_PRIORITY 12
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#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
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#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
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#define RT_LWIP_ETHTHREAD_PRIORITY 12
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#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
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#define LWIP_NETIF_STATUS_CALLBACK 1
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#define LWIP_NETIF_LINK_CALLBACK 1
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#define RT_LWIP_NETIF_NAMESIZE 6
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#define SO_REUSE 1
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#define LWIP_SO_RCVTIMEO 1
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#define LWIP_SO_SNDTIMEO 1
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#define LWIP_SO_RCVBUF 1
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#define LWIP_SO_LINGER 0
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#define LWIP_NETIF_LOOPBACK 0
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#define RT_LWIP_USING_PING
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/* Memory protection */
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/* Utilities */
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#define RT_USING_RYM
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#define YMODEM_USING_FILE_TRANSFER
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#define RT_USING_RESOURCE_ID
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#define RT_USING_ADT
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#define RT_USING_ADT_AVL
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#define RT_USING_ADT_BITMAP
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#define RT_USING_ADT_HASHMAP
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#define RT_USING_ADT_REF
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2023-11-21 17:42:23 +08:00
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2023-08-29 10:27:54 +08:00
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/* RT-Thread Utestcases */
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/* RT-Thread online packages */
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/* IoT - internet of things */
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/* Wi-Fi */
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/* Marvell WiFi */
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/* Wiced WiFi */
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/* IoT Cloud */
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/* security packages */
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/* language packages */
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/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
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/* XML: Extensible Markup Language */
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/* multimedia packages */
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/* LVGL: powerful and easy-to-use embedded GUI library */
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/* u8g2: a monochrome graphic library */
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/* tools packages */
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/* system packages */
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/* enhanced kernel services */
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/* acceleration: Assembly language or algorithmic acceleration packages */
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/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
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/* Micrium: Micrium software products porting for RT-Thread */
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/* peripheral libraries and drivers */
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/* sensors drivers */
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/* touch drivers */
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/* Kendryte SDK */
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/* AI packages */
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2024-01-13 23:01:55 +08:00
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/* Signal Processing and Control Algorithm Packages */
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2023-08-29 10:27:54 +08:00
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/* miscellaneous packages */
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/* project laboratory */
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/* samples: kernel and components samples */
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#define PKG_USING_KERNEL_SAMPLES
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#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
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#define PKG_USING_KERNEL_SAMPLES_EN
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/* entertainment: terminal games and other interesting software packages */
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/* Arduino libraries */
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2024-01-13 23:01:55 +08:00
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/* Projects and Demos */
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/* Sensors */
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/* Display */
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/* Timing */
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/* Data Processing */
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/* Data Storage */
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/* Communication */
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/* Device Control */
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/* Other */
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2024-01-13 23:01:55 +08:00
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/* Signal IO */
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/* Uncategorized */
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/* Hardware Drivers */
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2023-11-21 17:42:23 +08:00
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2023-08-29 10:27:54 +08:00
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/* On-chip Peripheral Drivers */
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2023-11-21 17:42:23 +08:00
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#define BSP_USING_IOPAD
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2023-08-29 10:27:54 +08:00
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#define BSP_USING_UART
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2023-12-08 17:57:55 +08:00
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#define RT_USING_UART0
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2023-08-29 10:27:54 +08:00
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#define RT_USING_UART1
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2023-12-08 17:57:55 +08:00
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#define BSP_USING_SPI
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#define RT_USING_SPIM0
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#define RT_USING_SPIM1
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#define RT_USING_SPIM2
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#define RT_USING_SPIM3
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#define BSP_USING_GPIO
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#define BSP_USING_QSPI
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#define RT_USING_QSPI0
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#define USING_QSPI_CHANNEL0
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2024-01-26 18:31:35 +08:00
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#define BSP_USING_ETH
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#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
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2023-12-08 17:57:55 +08:00
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#define BSP_USING_PWM
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#define RT_USING_PWM2
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#define BSP_USING_I2C
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#define I2C_USE_MIO
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#define RT_USING_MIO0
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#define RT_USING_MIO1
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#define RT_USING_MIO2
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#define RT_USING_MIO10
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2023-12-16 19:10:26 +08:00
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#define BSP_USING_DC
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2023-08-29 10:27:54 +08:00
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/* Board extended module Drivers */
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#define BSP_USING_GIC
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#define BSP_USING_GICV3
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#define PHYTIUM_ARCH_AARCH64
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2023-11-21 17:42:23 +08:00
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#define ARM_SPI_BIND_CPU_ID 2
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2023-08-29 10:27:54 +08:00
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/* Standalone Setting */
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#define TARGET_ARMV8_AARCH64
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2023-11-21 17:42:23 +08:00
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/* Soc configuration */
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2023-08-29 10:27:54 +08:00
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#define TARGET_PHYTIUMPI
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2023-11-21 17:42:23 +08:00
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#define SOC_NAME "phytiumpi"
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#define SOC_CORE_NUM 4
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#define F32BIT_MEMORY_ADDRESS 0x80000000
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#define F32BIT_MEMORY_LENGTH 0x80000000
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#define F64BIT_MEMORY_ADDRESS 0x2000000000
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#define F64BIT_MEMORY_LENGTH 0x800000000
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2023-08-29 10:27:54 +08:00
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#define TARGET_E2000
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#define DEFAULT_DEBUG_PRINT_UART1
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2023-11-21 17:42:23 +08:00
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/* Board Configuration */
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2023-08-29 10:27:54 +08:00
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2023-11-21 17:42:23 +08:00
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#define BOARD_NAME "firefly"
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#define FIREFLY_DEMO_BOARD
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2023-08-29 10:27:54 +08:00
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2023-11-21 17:42:23 +08:00
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/* IO mux configuration when board start up */
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2023-08-29 10:27:54 +08:00
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2023-11-21 17:42:23 +08:00
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/* Sdk common configuration */
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2023-08-29 10:27:54 +08:00
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2023-11-21 17:42:23 +08:00
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#define LOG_DEBUG
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2023-08-29 10:27:54 +08:00
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2023-11-21 17:42:23 +08:00
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/* Image information configuration */
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2023-08-29 10:27:54 +08:00
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#endif
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