691 lines
21 KiB
C
691 lines
21 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_PMU_H_
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#define _FSL_PMU_H_
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#include "fsl_common.h"
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/*! @addtogroup pmu */
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/*! @{ */
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief PMU driver version */
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#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
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/*@}*/
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/*!
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* @brief Status flags.
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*/
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enum _pmu_status_flags
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{
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kPMU_1P1RegulatorOutputOK = (1U << 0U), /*!< Status bit that signals when the 1p1 regulator output
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is ok. 1 = regulator output > brownout target. */
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kPMU_1P1BrownoutOnOutput = (1U << 1U), /*!< Status bit that signals when a 1p1 brownout is detected
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on the regulator output. */
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kPMU_3P0RegulatorOutputOK = (1U << 2U), /*!< Status bit that signals when the 3p0 regulator output
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is ok. 1 = regulator output > brownout target. */
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kPMU_3P0BrownoutOnOutput = (1U << 3U), /*!< Status bit that signals when a 3p0 brownout is detected
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on the regulator output. */
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kPMU_2P5RegulatorOutputOK = (1U << 4U), /*!< Status bit that signals when the 2p5 regulator output
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is ok. 1 = regulator output > brownout target. */
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kPMU_2P5BrownoutOnOutput = (1U << 5U), /*!< Status bit that signals when a 2p5 brownout is detected
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on the regulator output. */
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};
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/*!
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* @brief The source for the reference voltage of the weak 1P1 regulator.
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*/
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typedef enum _pmu_1p1_weak_reference_source
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{
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kPMU_1P1WeakReferenceSourceAlt0 = 0U, /*!< Weak-linreg output tracks low-power-bandgap voltage. */
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kPMU_1P1WeakReferenceSourceAlt1 = 1U, /*!< Weak-linreg output tracks VDD_SOC_CAP voltage. */
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} pmu_1p1_weak_reference_source_t;
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/*!
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* @brief Input voltage source for LDO_3P0 from USB VBus.
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*/
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typedef enum _pmu_3p0_vbus_voltage_source
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{
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kPMU_3P0VBusVoltageSourceAlt0 = 0U, /*!< USB_OTG1_VBUS - Utilize VBUS OTG1 for power. */
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kPMU_3P0VBusVoltageSourceAlt1 = 1U, /*!< USB_OTG2_VBUS - Utilize VBUS OTG2 for power. */
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} pmu_3p0_vbus_voltage_source_t;
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/*!
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* @brief Regulator voltage ramp rate.
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*/
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typedef enum _pmu_core_reg_voltage_ramp_rate
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{
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kPMU_CoreRegVoltageRampRateFast = 0U, /*!< Fast. */
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kPMU_CoreRegVoltageRampRateMediumFast = 1U, /*!< Medium Fast. */
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kPMU_CoreRegVoltageRampRateMediumSlow = 2U, /*!< Medium Slow. */
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kPMU_CoreRegVoltageRampRateSlow = 0U, /*!< Slow. */
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} pmu_core_reg_voltage_ramp_rate_t;
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#if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL
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/*!
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* @brief Mask values of power gate.
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*/
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enum _pmu_power_gate
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{
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kPMU_PowerGateDisplay = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK, /*!< Display power gate control. */
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kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK, /*!< Display logic power gate control. */
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kPMU_PowerGateL2 = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK, /*!< L2 power gate control. */
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kPMU_PowerGateL1 = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK, /*!< L1 power gate control. */
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kPMU_PowerGateRefTopIBias = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */
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};
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#endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */
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/*!
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* @brief Bandgap select.
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*/
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typedef enum _pmu_power_bandgap
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{
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kPMU_NormalPowerBandgap = 0U, /*!< Normal power bandgap. */
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kPMU_LowPowerBandgap = 1U, /*!< Low power bandgap. */
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} pmu_power_bandgap_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @name Status.
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* @{
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*/
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uint32_t PMU_GetStatusFlags(PMU_Type *base);
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/*@}*/
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/*!
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* @name 1P1 Regular
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* @{
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*/
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/*!
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* @brief Selects the source for the reference voltage of the weak 1P1 regulator.
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*
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* @param base PMU peripheral base address.
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* @param option The option for reference voltage source, see to #pmu_1p1_weak_reference_source_t.
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*/
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static inline void PMU_1P1SetWeakReferenceSource(PMU_Type *base, pmu_1p1_weak_reference_source_t option)
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{
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base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) | PMU_REG_1P1_SELREF_WEAK_LINREG(option);
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}
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/*!
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* @brief Enables the weak 1P1 regulator.
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*
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* This regulator can be used when the main 1P1 regulator is disabled, under low-power conditions.
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*
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* @param base PMU peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void PMU_1P1EnableWeakRegulator(PMU_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG_1P1 |= PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
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}
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else
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{
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base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK;
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}
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}
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/*!
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* @brief Adjust the 1P1 regulator output voltage.
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*
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* Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
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* may be interpolated from these examples. Choices must be in this range:
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* - 0x1b(1.375V) >= output_trg >= 0x04(0.8V)
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* - 0x04 : 0.8V
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* - 0x10 : 1.1V (typical)
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* - 0x1b : 1.375V
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* NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range.
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*
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* @param base PMU peripheral base address.
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* @param value Setting value for the output.
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*/
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static inline void PMU_1P1SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
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{
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base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_OUTPUT_TRG_MASK) | PMU_REG_1P1_OUTPUT_TRG(value);
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}
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/*!
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* @brief Adjust the 1P1 regulator brownout offset voltage.
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*
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* Control bits to adjust the regulator brownout offset voltage in 25mV steps. The reset
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* brown-offset is 175mV below the programmed target code.
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* Brownout target = OUTPUT_TRG - BO_OFFSET.
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* Some steps may be irrelevant because of input supply limitations or load operation.
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*
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* @param base PMU peripheral base address.
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* @param value Setting value for the brownout offset. The available range is in 3-bit.
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*/
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static inline void PMU_1P1SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
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{
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base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_BO_OFFSET_MASK) | PMU_REG_1P1_BO_OFFSET(value);
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}
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/*!
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* @brief Enable the pull-down circuitry in the regulator.
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*
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* @param base PMU peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void PMU_1P1EnablePullDown(PMU_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG_1P1 |= PMU_REG_1P1_ENABLE_PULLDOWN_MASK;
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}
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else
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{
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base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_PULLDOWN_MASK;
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}
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}
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/*!
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* @brief Enable the current-limit circuitry in the regulator.
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*
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* @param base PMU peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void PMU_1P1EnableCurrentLimit(PMU_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG_1P1 |= PMU_REG_1P1_ENABLE_ILIMIT_MASK;
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}
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else
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{
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base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_ILIMIT_MASK;
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}
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}
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/*!
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* @brief Enable the brownout circuitry in the regulator.
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*
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* @param base PMU peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void PMU_1P1EnableBrownout(PMU_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG_1P1 |= PMU_REG_1P1_ENABLE_BO_MASK;
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}
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else
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{
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base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_BO_MASK;
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}
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}
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/*!
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* @brief Enable the regulator output.
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*
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* @param base PMU peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void PMU_1P1EnableOutput(PMU_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG_1P1 |= PMU_REG_1P1_ENABLE_LINREG_MASK;
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}
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else
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{
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base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_LINREG_MASK;
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}
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}
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/*@}*/
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/*!
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* @name 3P0 Regular
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* @{
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*/
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/*!
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* @brief Adjust the 3P0 regulator output voltage.
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*
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* Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
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* may be interpolated from these examples. Choices must be in this range:
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* - 0x00(2.625V) >= output_trg >= 0x1f(3.4V)
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* - 0x00 : 2.625V
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* - 0x0f : 3.0V (typical)
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* - 0x1f : 3.4V
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*
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* @param base PMU peripheral base address.
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* @param value Setting value for the output.
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*/
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static inline void PMU_3P0SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
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{
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base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_OUTPUT_TRG_MASK) | PMU_REG_3P0_OUTPUT_TRG(value);
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}
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/*!
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* @brief Select input voltage source for LDO_3P0.
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*
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* Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS. If only
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* one of the two VBUS voltages is present, it is automatically selected.
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*
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* @param base PMU peripheral base address.
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* @param option User-defined input voltage source for LDO_3P0.
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*/
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static inline void PMU_3P0SetVBusVoltageSource(PMU_Type *base, pmu_3p0_vbus_voltage_source_t option)
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{
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base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_VBUS_SEL_MASK) | PMU_REG_3P0_VBUS_SEL(option);
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}
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/*!
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* @brief Adjust the 3P0 regulator brownout offset voltage.
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*
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* Control bits to adjust the 3P0 regulator brownout offset voltage in 25mV steps. The reset
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* brown-offset is 175mV below the programmed target code.
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* Brownout target = OUTPUT_TRG - BO_OFFSET.
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* Some steps may be irrelevant because of input supply limitations or load operation.
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*
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* @param base PMU peripheral base address.
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* @param value Setting value for the brownout offset. The available range is in 3-bit.
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*/
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static inline void PMU_3P0SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
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{
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base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_BO_OFFSET_MASK) | PMU_REG_3P0_BO_OFFSET(value);
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}
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/*!
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* @brief Enable the current-limit circuitry in the 3P0 regulator.
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*
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* @param base PMU peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void PMU_3P0EnableCurrentLimit(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_3P0 |= PMU_REG_3P0_ENABLE_ILIMIT_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_ILIMIT_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the brownout circuitry in the 3P0 regulator.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void PMU_3P0EnableBrownout(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_3P0 |= PMU_REG_3P0_ENABLE_BO_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_BO_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the 3P0 regulator output.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void PMU_3P0EnableOutput(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_3P0 |= PMU_REG_3P0_ENABLE_LINREG_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_LINREG_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name 2P5 Regulator
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enables the weak 2P5 regulator.
|
||
|
|
*
|
||
|
|
* This low power regulator is used when the main 2P5 regulator is disabled
|
||
|
|
* to keep the 2.5V output roughly at 2.5V. Scales directly with the value of VDDHIGH_IN.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void PMU_2P5EnableWeakRegulator(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_2P5 |= PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Adjust the 1P1 regulator output voltage.
|
||
|
|
*
|
||
|
|
* Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages
|
||
|
|
* may be interpolated from these examples. Choices must be in this range:
|
||
|
|
* - 0x00(2.1V) >= output_trg >= 0x1f(2.875V)
|
||
|
|
* - 0x00 : 2.1V
|
||
|
|
* - 0x10 : 2.5V (typical)
|
||
|
|
* - 0x1f : 2.875V
|
||
|
|
* NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param value Setting value for the output.
|
||
|
|
*/
|
||
|
|
static inline void PMU_2P5SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value)
|
||
|
|
{
|
||
|
|
base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Adjust the 2P5 regulator brownout offset voltage.
|
||
|
|
*
|
||
|
|
* Adjust the regulator brownout offset voltage in 25mV steps. The reset
|
||
|
|
* brown-offset is 175mV below the programmed target code.
|
||
|
|
* Brownout target = OUTPUT_TRG - BO_OFFSET.
|
||
|
|
* Some steps may be irrelevant because of input supply limitations or load operation.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param value Setting value for the brownout offset. The available range is in 3-bit.
|
||
|
|
*/
|
||
|
|
static inline void PMU_2P5SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value)
|
||
|
|
{
|
||
|
|
base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_BO_OFFSET_MASK) | PMU_REG_2P5_BO_OFFSET(value);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the pull-down circuitry in the 2P5 regulator.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void PMU_2P5EnablePullDown(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the pull-down circuitry in the 2P5 regulator.
|
||
|
|
* @deprecated Do not use this function. It has been superceded by @ref PMU_2P5EnablePullDown.
|
||
|
|
*/
|
||
|
|
static inline void PMU_2P1EnablePullDown(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the current-limit circuitry in the 2P5 regulator.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void PMU_2P5EnableCurrentLimit(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_2P5 |= PMU_REG_2P5_ENABLE_ILIMIT_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_ILIMIT_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the brownout circuitry in the 2P5 regulator.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void PMU_2P5nableBrownout(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_2P5 |= PMU_REG_2P5_ENABLE_BO_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_BO_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the 2P5 regulator output.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void PMU_2P5EnableOutput(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_2P5 |= PMU_REG_2P5_ENABLE_LINREG_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_LINREG_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @name Core Regulator
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Increase the gate drive on power gating FETs.
|
||
|
|
*
|
||
|
|
* If set, increases the gate drive on power gating FETs to reduce leakage in the off state.
|
||
|
|
* Care must be taken to apply this bit only when the input supply voltage to the power FET
|
||
|
|
* is less than 1.1V.
|
||
|
|
* NOTE: This bit should only be used in low-power modes where the external input supply voltage
|
||
|
|
* is nominally 0.9V.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the feature or not.
|
||
|
|
*/
|
||
|
|
static inline void PMU_CoreEnableIncreaseGateDrive(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->REG_CORE |= PMU_REG_CORE_FET_ODRIVE_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->REG_CORE &= ~PMU_REG_CORE_FET_ODRIVE_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Set the CORE regulator voltage ramp rate.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param option User-defined option for voltage ramp rate, see to #pmu_core_reg_voltage_ramp_rate_t.
|
||
|
|
*/
|
||
|
|
static inline void PMU_CoreSetRegulatorVoltageRampRate(PMU_Type *base, pmu_core_reg_voltage_ramp_rate_t option)
|
||
|
|
{
|
||
|
|
base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_RAMP_RATE_MASK) | PMU_REG_CORE_RAMP_RATE(option);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Define the target voltage for the SOC power domain.
|
||
|
|
*
|
||
|
|
* Define the target voltage for the SOC power domain. Single-bit increments reflect 25mV core
|
||
|
|
* voltage steps. Some steps may not be relevant because of input supply limitations or load operation.
|
||
|
|
* - 0x00 : Power gated off.
|
||
|
|
* - 0x01 : Target core voltage = 0.725V
|
||
|
|
* - 0x02 : Target core voltage = 0.750V
|
||
|
|
* - ...
|
||
|
|
* - 0x10 : Target core voltage = 1.100V
|
||
|
|
* - ...
|
||
|
|
* - 0x1e : Target core voltage = 1.450V
|
||
|
|
* - 0x1F : Power FET switched full on. No regulation.
|
||
|
|
* NOTE: This register is capable of programming an over-voltage condition on the device. Consult the
|
||
|
|
* datasheet Operating Ranges table for the allowed voltages.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param value Setting value for target voltage. 5-bit available
|
||
|
|
*/
|
||
|
|
static inline void PMU_CoreSetSOCDomainVoltage(PMU_Type *base, uint32_t value)
|
||
|
|
{
|
||
|
|
base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG2_TARG_MASK) | PMU_REG_CORE_REG2_TARG(value);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Define the target voltage for the ARM Core power domain.
|
||
|
|
*
|
||
|
|
* Define the target voltage for the ARM Core power domain. Single-bit increments reflect 25mV core
|
||
|
|
* voltage steps. Some steps may not be relevant because of input supply limitations or load operation.
|
||
|
|
* - 0x00 : Power gated off.
|
||
|
|
* - 0x01 : Target core voltage = 0.725V
|
||
|
|
* - 0x02 : Target core voltage = 0.750V
|
||
|
|
* - ...
|
||
|
|
* - 0x10 : Target core voltage = 1.100V
|
||
|
|
* - ...
|
||
|
|
* - 0x1e : Target core voltage = 1.450V
|
||
|
|
* - 0x1F : Power FET switched full on. No regulation.
|
||
|
|
* NOTE: This register is capable of programming an over-voltage condition on the device. Consult the
|
||
|
|
* datasheet Operating Ranges table for the allowed voltages.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param value Setting value for target voltage. 5-bit available
|
||
|
|
*/
|
||
|
|
static inline void PMU_CoreSetARMCoreDomainVoltage(PMU_Type *base, uint32_t value)
|
||
|
|
{
|
||
|
|
base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG0_TARG_MASK) | PMU_REG_CORE_REG0_TARG(value);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
#if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL
|
||
|
|
/*!
|
||
|
|
* @name Power Gate Controller & other
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Gate the power to modules.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param gates Mask value for the module to be gated. See to #_pmu_power_gate.
|
||
|
|
*/
|
||
|
|
static inline void PMU_GatePower(PMU_Type *base, uint32_t gates)
|
||
|
|
{
|
||
|
|
base->LOWPWR_CTRL_SET = gates;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Ungate the power to modules.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param gates Mask value for the module to be gated. See to #_pmu_power_gate.
|
||
|
|
*/
|
||
|
|
static inline void PMU_UngatePower(PMU_Type *base, uint32_t gates)
|
||
|
|
{
|
||
|
|
base->LOWPWR_CTRL_CLR = gates;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Enable the low power bandgap.
|
||
|
|
*
|
||
|
|
* @param base PMU peripheral base address.
|
||
|
|
* @param enable Enable the low power bandgap or use the normal power bandgap.
|
||
|
|
* @
|
||
|
|
*/
|
||
|
|
static inline void PMU_EnableLowPowerBandgap(PMU_Type *base, bool enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
base->LOWPWR_CTRL_SET = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the low power bandgap. */
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->LOWPWR_CTRL_CLR = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the normal power bandgap. */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif /* __cplusplus*/
|
||
|
|
|
||
|
|
/*! @}*/
|
||
|
|
|
||
|
|
#endif /* _FSL_PMU_H_*/
|