2017-08-22 15:52:57 +08:00
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/*!
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2021-06-09 16:24:20 +08:00
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\file gd32f4xx_spi.h
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\brief definitions for the SPI
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\version 2016-08-15, V1.0.0, firmware for GD32F4xx
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\version 2018-12-12, V2.0.0, firmware for GD32F4xx
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\version 2020-09-30, V2.1.0, firmware for GD32F4xx
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2017-08-22 15:52:57 +08:00
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*/
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/*
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2021-06-09 16:24:20 +08:00
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Copyright (c) 2020, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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2017-08-22 15:52:57 +08:00
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*/
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2021-06-09 16:24:20 +08:00
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2017-08-22 15:52:57 +08:00
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#ifndef GD32F4XX_SPI_H
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#define GD32F4XX_SPI_H
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#include "gd32f4xx.h"
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/* SPIx(x=0,1,2,3,4,5) definitions */
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#define SPI0 (SPI_BASE + 0x0000F800U)
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#define SPI1 SPI_BASE
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#define SPI2 (SPI_BASE + 0x00000400U)
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#define SPI3 (SPI_BASE + 0x0000FC00U)
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#define SPI4 (SPI_BASE + 0x00011800U)
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#define SPI5 (SPI_BASE + 0x00011C00U)
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/* I2Sx_ADD(x=1,2) definitions */
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#define I2S1_ADD I2S_ADD_BASE
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#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U)
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/* SPI registers definitions */
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#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */
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#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/
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#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */
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#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */
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#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */
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#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */
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#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */
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#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */
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#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */
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#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register */
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/* I2S_ADD registers definitions */
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#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00U) /*!< I2S_ADD control register 0 */
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#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x04U) /*!< I2S_ADD control register 1*/
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#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x08U) /*!< I2S_ADD status register */
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#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0CU) /*!< I2S_ADD data register */
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#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x10U) /*!< I2S_ADD CRC polynomial register */
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#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x14U) /*!< I2S_ADD receive CRC register */
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#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x18U) /*!< I2S_ADD transmit CRC register */
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#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x1CU) /*!< I2S_ADD I2S control register */
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#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x20U) /*!< I2S_ADD I2S clock prescaler register */
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/* bits definitions */
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/* SPI_CTL0 */
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#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
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#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
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#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
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#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
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#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
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#define SPI_CTL0_LF BIT(7) /*!< lsb first mode */
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#define SPI_CTL0_SWNSS BIT(8) /*!< nss pin selection in nss software mode */
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#define SPI_CTL0_SWNSSEN BIT(9) /*!< nss software mode selection */
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#define SPI_CTL0_RO BIT(10) /*!< receive only */
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#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
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#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
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#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
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#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
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#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
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/* SPI_CTL1 */
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#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */
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#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */
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#define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */
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#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
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#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
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#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
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#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
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/* SPI_STAT */
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#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
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#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
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#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
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#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
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#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
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#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
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#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
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#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
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#define SPI_STAT_FERR BIT(8) /*!< format error bit */
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/* SPI_DATA */
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#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
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/* SPI_CRCPOLY */
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#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */
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/* SPI_RCRC */
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#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */
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/* SPI_TCRC */
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#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */
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/* SPI_I2SCTL */
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#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
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#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
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#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
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#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
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#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
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#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
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#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
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#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
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/* SPI_I2S_PSC */
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#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
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#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
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#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
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/* SPI_SPI_QCTL(only SPI5) */
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#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
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#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
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#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
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/* constants definitions */
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/* SPI and I2S parameter struct definitions */
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typedef struct
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{
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uint32_t device_mode; /*!< SPI master or slave */
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uint32_t trans_mode; /*!< SPI transtype */
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uint32_t frame_size; /*!< SPI frame size */
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uint32_t nss; /*!< SPI nss control by handware or software */
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uint32_t endian; /*!< SPI big endian or little endian */
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uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
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uint32_t prescale; /*!< SPI prescale factor */
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}spi_parameter_struct;
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/* SPI mode definitions */
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#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
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#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
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/* SPI bidirectional transfer direction */
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#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
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#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
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/* SPI transmit type */
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#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
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#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
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#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
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#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
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/* SPI frame size */
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#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
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#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
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/* SPI NSS control mode */
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#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI nss control by sofrware */
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#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI nss control by hardware */
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/* SPI transmit way */
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#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
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#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
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/* SPI clock polarity and phase */
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#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
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#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
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#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
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#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL|SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
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/* SPI clock prescale factor */
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#define CTL0_PSC(regval) (BITS(3,5)&((uint32_t)(regval)<<3))
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#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */
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#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */
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#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */
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#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */
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#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */
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#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */
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#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */
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#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */
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/* I2S audio sample rate */
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#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
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#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
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#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
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#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
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#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
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#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
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#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
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#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
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#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
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/* I2S frame format */
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#define I2SCTL_DTLEN(regval) (BITS(1,2)&((uint32_t)(regval)<<1))
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#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
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#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
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#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
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#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
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/* I2S master clock output */
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#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
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#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
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2021-06-09 16:24:20 +08:00
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/* I2S operation mode */
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2017-08-22 15:52:57 +08:00
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#define I2SCTL_I2SOPMOD(regval) (BITS(8,9)&((uint32_t)(regval)<<8))
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#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
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#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
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#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
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#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
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2021-06-09 16:24:20 +08:00
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/* I2S standard */
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2017-08-22 15:52:57 +08:00
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#define I2SCTL_I2SSTD(regval) (BITS(4,5)&((uint32_t)(regval)<<4))
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#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
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#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
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#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
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#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
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2021-06-09 16:24:20 +08:00
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#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
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2017-08-22 15:52:57 +08:00
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2021-06-09 16:24:20 +08:00
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/* I2S clock polarity */
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2017-08-22 15:52:57 +08:00
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#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
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#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
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2021-06-09 16:24:20 +08:00
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/* SPI DMA constants definitions */
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#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
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#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
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2017-08-22 15:52:57 +08:00
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/* SPI CRC constants definitions */
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#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
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#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
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2021-06-09 16:24:20 +08:00
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/* SPI/I2S interrupt enable/disable constants definitions */
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2017-08-22 15:52:57 +08:00
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#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */
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#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */
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2021-06-09 16:24:20 +08:00
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#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */
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/* SPI/I2S interrupt flag constants definitions */
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#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
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#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
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#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
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#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
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#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
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#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
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#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
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/* SPI/I2S flag definitions */
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2017-08-22 15:52:57 +08:00
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#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
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#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
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#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
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#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
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#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
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#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
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#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
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2017-08-22 15:52:57 +08:00
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#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
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#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
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#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
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#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
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#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
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#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
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#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
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2017-08-22 15:52:57 +08:00
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/* function declarations */
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/* initialization functions */
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/* deinitialize SPI and I2S */
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2017-08-22 15:52:57 +08:00
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void spi_i2s_deinit(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* initialize the parameters of SPI struct with the default values */
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void spi_struct_para_init(spi_parameter_struct* spi_struct);
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/* initialize SPI parameter */
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2017-08-22 15:52:57 +08:00
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void spi_init(uint32_t spi_periph,spi_parameter_struct* spi_struct);
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/* enable SPI */
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2017-08-22 15:52:57 +08:00
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void spi_enable(uint32_t spi_periph);
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/* disable SPI */
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2017-08-22 15:52:57 +08:00
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void spi_disable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* initialize I2S parameter */
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2017-08-22 15:52:57 +08:00
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void i2s_init(uint32_t spi_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl);
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/* configure I2S prescale */
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2017-08-22 15:52:57 +08:00
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void i2s_psc_config(uint32_t spi_periph,uint32_t i2s_audiosample,uint32_t i2s_frameformat,uint32_t i2s_mckout);
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2021-06-09 16:24:20 +08:00
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/* enable I2S */
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2017-08-22 15:52:57 +08:00
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void i2s_enable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* disable I2S */
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2017-08-22 15:52:57 +08:00
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void i2s_disable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* NSS functions */
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/* enable SPI nss output */
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2017-08-22 15:52:57 +08:00
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void spi_nss_output_enable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* disable SPI nss output */
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2017-08-22 15:52:57 +08:00
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void spi_nss_output_disable(uint32_t spi_periph);
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/* SPI nss pin high level in software mode */
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void spi_nss_internal_high(uint32_t spi_periph);
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/* SPI nss pin low level in software mode */
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void spi_nss_internal_low(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* SPI DMA functions */
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/* enable SPI DMA */
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2017-08-22 15:52:57 +08:00
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void spi_dma_enable(uint32_t spi_periph,uint8_t spi_dma);
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2021-06-09 16:24:20 +08:00
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/* disable SPI DMA */
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2017-08-22 15:52:57 +08:00
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void spi_dma_disable(uint32_t spi_periph,uint8_t spi_dma);
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2021-06-09 16:24:20 +08:00
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/* SPI/I2S transfer configure functions */
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2017-08-22 15:52:57 +08:00
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/* configure SPI/I2S data frame format */
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void spi_i2s_data_frame_format_config(uint32_t spi_periph,uint16_t frame_format);
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2021-06-09 16:24:20 +08:00
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/* SPI transmit data */
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2017-08-22 15:52:57 +08:00
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void spi_i2s_data_transmit(uint32_t spi_periph,uint16_t data);
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2021-06-09 16:24:20 +08:00
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/* SPI receive data */
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2017-08-22 15:52:57 +08:00
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uint16_t spi_i2s_data_receive(uint32_t spi_periph);
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/* configure SPI bidirectional transfer direction */
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void spi_bidirectional_transfer_config(uint32_t spi_periph,uint32_t transfer_direction);
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2021-06-09 16:24:20 +08:00
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/* SPI CRC functions */
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/* set SPI CRC polynomial */
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2017-08-22 15:52:57 +08:00
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void spi_crc_polynomial_set(uint32_t spi_periph,uint16_t crc_poly);
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2021-06-09 16:24:20 +08:00
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/* get SPI CRC polynomial */
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2017-08-22 15:52:57 +08:00
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uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* turn on SPI CRC function */
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2017-08-22 15:52:57 +08:00
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void spi_crc_on(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* turn off SPI CRC function */
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2017-08-22 15:52:57 +08:00
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void spi_crc_off(uint32_t spi_periph);
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/* SPI next data is CRC value */
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void spi_crc_next(uint32_t spi_periph);
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/* get SPI CRC send value or receive value */
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uint16_t spi_crc_get(uint32_t spi_periph,uint8_t spi_crc);
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2021-06-09 16:24:20 +08:00
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/* SPI TI mode functions */
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/* enable SPI TI mode */
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2017-08-22 15:52:57 +08:00
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void spi_ti_mode_enable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* disable SPI TI mode */
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2017-08-22 15:52:57 +08:00
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void spi_ti_mode_disable(uint32_t spi_periph);
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/* configure i2s full duplex mode */
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void i2s_full_duplex_mode_config(uint32_t i2s_add_periph,uint32_t i2s_mode,uint32_t i2s_standard,uint32_t i2s_ckpl,uint32_t i2s_frameformat);
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2021-06-09 16:24:20 +08:00
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/* quad wire SPI functions */
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/* enable quad wire SPI */
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2017-08-22 15:52:57 +08:00
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void qspi_enable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* disable quad wire SPI */
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2017-08-22 15:52:57 +08:00
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void qspi_disable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* enable quad wire SPI write */
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2017-08-22 15:52:57 +08:00
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void qspi_write_enable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* enable quad wire SPI read */
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2017-08-22 15:52:57 +08:00
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void qspi_read_enable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
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2017-08-22 15:52:57 +08:00
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void qspi_io23_output_enable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
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2017-08-22 15:52:57 +08:00
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void qspi_io23_output_disable(uint32_t spi_periph);
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2021-06-09 16:24:20 +08:00
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/* flag & interrupt functions */
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/* enable SPI interrupt */
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void spi_i2s_interrupt_enable(uint32_t spi_periph,uint8_t spi_i2s_int);
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/* disable SPI interrupt */
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void spi_i2s_interrupt_disable(uint32_t spi_periph,uint8_t spi_i2s_int);
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/* get SPI and I2S interrupt status*/
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FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph,uint8_t spi_i2s_int);
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/* get SPI and I2S flag status */
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FlagStatus spi_i2s_flag_get(uint32_t spi_periph,uint32_t spi_i2s_flag);
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/* clear SPI CRC error flag status */
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void spi_crc_error_clear(uint32_t spi_periph);
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2017-08-22 15:52:57 +08:00
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#endif /* GD32F4XX_SPI_H */
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