2017-11-17 20:07:04 +08:00
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-09-22 Bernard add board.h to this bsp
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2017-12-29 06:05:42 +08:00
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* 2017-12-29 ZYH Correctly generate the 48M clock
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2017-11-17 20:07:04 +08:00
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*/
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#include <rtthread.h>
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#include "board.h"
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/**
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* @addtogroup STM32
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*/
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/*@{*/
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2017-12-29 06:05:42 +08:00
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#if defined(RCC_PERIPHCLK_SDIO) || defined(RCC_PERIPHCLK_CEC) || defined(RCC_PERIPHCLK_LTDC)\
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|| defined(RCC_PERIPHCLK_SPDIFRX) || defined(RCC_PERIPHCLK_FMPI2C1) || defined(RCC_PERIPHCLK_LPTIM1)
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2018-04-18 09:47:49 +08:00
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#warning Please give priority to the correctness of the clock tree when the peripherals are abnormal
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2017-12-29 06:05:42 +08:00
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#endif
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2018-04-18 09:47:49 +08:00
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2017-11-17 20:07:04 +08:00
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static void SystemClock_Config(void)
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{
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2018-07-14 19:42:44 +08:00
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rt_uint32_t source_clk, sys_clk;
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#if !defined(RT_USING_HSI) && (RT_HSE_VALVE % 1000000 != 0)
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2018-04-18 09:47:49 +08:00
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#error HSE must be integer of MHz
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2017-12-29 06:05:42 +08:00
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#endif
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2018-07-14 19:42:44 +08:00
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#ifdef RT_USING_HSI
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#define CLOCK_SOURE_VALUE HSI_VALUE
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#else
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#define CLOCK_SOURE_VALUE HSE_VALUE
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#endif
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source_clk = CLOCK_SOURE_VALUE / 1000000UL;
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2018-04-18 09:47:49 +08:00
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sys_clk = HCLK_VALUE / 1000000UL;
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2017-12-12 01:43:17 +08:00
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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2017-12-29 06:05:42 +08:00
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#if defined(RT_USING_RTC) || defined(RCC_PERIPHCLK_CLK48)
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2017-12-12 01:43:17 +08:00
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
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#endif
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2018-04-18 09:47:49 +08:00
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/**Configure the main internal regulator output voltage
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2017-11-17 20:07:04 +08:00
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*/
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2017-12-12 01:43:17 +08:00
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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2018-04-18 09:47:49 +08:00
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/**Initializes the CPU, AHB and APB busses clocks
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2017-11-17 20:07:04 +08:00
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*/
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2018-07-14 19:42:44 +08:00
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#ifdef RT_USING_HSI
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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#else
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2017-12-12 01:43:17 +08:00
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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2018-07-14 19:42:44 +08:00
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#endif
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2017-12-12 01:43:17 +08:00
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#ifdef RT_USING_RTC
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSI;
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RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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#endif
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2018-07-14 19:42:44 +08:00
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#ifdef RT_USING_HSI
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = source_clk;
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#else
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2018-07-05 17:11:53 +08:00
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#ifdef BSP_HSE_BY_PASS
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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2018-07-14 19:42:44 +08:00
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#else
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2017-12-12 01:43:17 +08:00
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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2018-07-14 19:42:44 +08:00
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#endif
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2018-07-05 17:11:53 +08:00
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#endif
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2017-12-12 01:43:17 +08:00
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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2018-07-14 19:42:44 +08:00
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#ifdef RT_USING_HSI
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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#else
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2017-12-12 01:43:17 +08:00
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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2018-07-14 19:42:44 +08:00
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#endif
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if (source_clk % 2 == 0)
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2017-12-29 06:05:42 +08:00
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{
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2018-07-14 19:42:44 +08:00
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RCC_OscInitStruct.PLL.PLLM = source_clk / 2; //Get 2M clock
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if ((sys_clk * 4) % 48 == 0)
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2017-12-29 06:05:42 +08:00
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 2;//Get 4*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;//Get HCLK_VALUE
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}
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2018-04-18 09:47:49 +08:00
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else if ((sys_clk * 6) % 48 == 0)
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2017-12-29 06:05:42 +08:00
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 3;//Get 6*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV6;//Get HCLK_VALUE
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}
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2018-04-18 09:47:49 +08:00
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else if ((sys_clk * 8) % 48 == 0)
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2017-12-29 06:05:42 +08:00
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 4;//Get 8*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV8;//Get HCLK_VALUE
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}
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2018-07-14 19:42:44 +08:00
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else
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2017-12-29 06:05:42 +08:00
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{
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2018-07-14 19:42:44 +08:00
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//can not get 48M Clock USB is unuseable
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RCC_OscInitStruct.PLL.PLLN = sys_clk;//Get 2*HCLK_VALUE
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2017-12-29 06:05:42 +08:00
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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}
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2018-07-14 19:42:44 +08:00
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}
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else
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{
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RCC_OscInitStruct.PLL.PLLM = source_clk;//Get 1M clock
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if ((sys_clk * 4) % 48 == 0)
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2017-12-29 06:05:42 +08:00
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 4;//Get 4*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;//Get HCLK_VALUE
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}
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2018-04-18 09:47:49 +08:00
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else if ((sys_clk * 6) % 48 == 0)
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2017-12-29 06:05:42 +08:00
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 6;//Get 6*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV6;//Get HCLK_VALUE
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}
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2018-04-18 09:47:49 +08:00
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else if ((sys_clk * 8) % 48 == 0)
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2017-12-29 06:05:42 +08:00
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{
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 8;//Get 8*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV8;//Get HCLK_VALUE
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}
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2018-07-14 19:42:44 +08:00
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else
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{
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//can not get 48M Clock USB is unuseable
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RCC_OscInitStruct.PLL.PLLN = sys_clk * 2;//Get 2*HCLK_VALUE
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;//Get HCLK_VALUE
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}
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2017-12-29 06:05:42 +08:00
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}
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2018-07-14 19:42:44 +08:00
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RCC_OscInitStruct.PLL.PLLQ = source_clk / RCC_OscInitStruct.PLL.PLLM * RCC_OscInitStruct.PLL.PLLN / 48; //Get 48M Clock
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2017-12-12 01:43:17 +08:00
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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2018-04-18 09:47:49 +08:00
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while (1)
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2017-12-12 01:43:17 +08:00
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{}
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}
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2018-04-18 09:47:49 +08:00
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/**Initializes the CPU, AHB and APB busses clocks
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2017-11-17 20:07:04 +08:00
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*/
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2018-04-18 09:47:49 +08:00
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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2017-12-12 01:43:17 +08:00
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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#if (RT_HSE_HCLK <= 42000000UL)
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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{
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2018-04-18 09:47:49 +08:00
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while (1)
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2017-12-12 01:43:17 +08:00
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{}
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}
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#elif (RT_HSE_HCLK <= 84000000UL)
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
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{
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2018-04-18 09:47:49 +08:00
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while (1)
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2017-12-12 01:43:17 +08:00
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{}
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}
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2018-07-14 19:42:44 +08:00
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#elif (RT_HSE_HCLK <= 100000000UL)
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
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{
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while (1)
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{}
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}
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2017-12-12 01:43:17 +08:00
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#elif (RT_HSE_HCLK <= 168000000UL)
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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2018-04-18 09:47:49 +08:00
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while (1)
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2017-12-12 01:43:17 +08:00
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{}
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}
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#else
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV8;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
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{
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2018-04-18 09:47:49 +08:00
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while (1)
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2017-12-12 01:43:17 +08:00
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{}
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}
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#endif
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2017-12-29 06:05:42 +08:00
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#if defined(RT_USING_RTC) || defined(RCC_PERIPHCLK_CLK48)
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PeriphClkInitStruct.PeriphClockSelection = 0;
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2018-04-18 09:47:49 +08:00
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#ifdef RT_USING_RTC
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2017-12-29 06:05:42 +08:00
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PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_RTC;
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2017-12-12 01:43:17 +08:00
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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2018-04-18 09:47:49 +08:00
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#endif
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#ifdef RCC_PERIPHCLK_CLK48
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2017-12-29 06:05:42 +08:00
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PeriphClkInitStruct.PeriphClockSelection |= RCC_PERIPHCLK_CLK48;
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PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
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2018-04-18 09:47:49 +08:00
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#endif
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2017-12-12 01:43:17 +08:00
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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2018-04-18 09:47:49 +08:00
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while (1)
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2017-12-12 01:43:17 +08:00
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{}
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}
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#endif
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2017-11-17 20:07:04 +08:00
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}
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2018-04-18 09:47:49 +08:00
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2017-11-17 20:07:04 +08:00
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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/* tick for HAL Library */
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HAL_IncTick();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/* re-implementat tick interface for STM32 HAL */
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HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
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{
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/*Configure the SysTick to have interrupt in 1ms time basis*/
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
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/*Configure the SysTick IRQ priority */
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2018-04-18 09:47:49 +08:00
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HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0);
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2017-11-17 20:07:04 +08:00
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/* Return function status */
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return HAL_OK;
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}
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void HAL_Delay(__IO uint32_t Delay)
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{
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rt_thread_delay(Delay);
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}
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void HAL_SuspendTick(void)
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{
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/* we should not suspend tick */
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}
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void HAL_ResumeTick(void)
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{
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/* we should not resume tick */
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}
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2018-04-18 09:47:49 +08:00
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2017-11-17 20:07:04 +08:00
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void HAL_MspInit(void)
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{
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2018-04-18 09:47:49 +08:00
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HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
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/* System interrupt init*/
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/* MemoryManagement_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0);
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/* BusFault_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0);
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/* UsageFault_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0);
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/* SVCall_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0);
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/* DebugMonitor_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0);
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/* PendSV_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
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/* SysTick_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
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2017-11-17 20:07:04 +08:00
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}
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/**
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* This function will initial STM32 board.
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*/
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void rt_hw_board_init()
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{
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/* Configure the system clock @ 84 Mhz */
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SystemClock_Config();
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HAL_Init();
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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}
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