784 lines
24 KiB
C
784 lines
24 KiB
C
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/*!
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\file system_gd32f3x0.c
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\brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
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GD32F3x0 Device Series
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*/
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/* Copyright (c) 2012 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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#include "gd32f3x0.h"
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/* system frequency define */
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#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
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#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
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#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
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#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
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/* select a system clock by uncommenting the following line */
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#if defined (GD32F330)
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//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
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//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
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//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
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//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
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//#define __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2 (uint32_t)(72000000)
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#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000)
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//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000)
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#endif /* GD32F330 */
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#if defined (GD32F350)
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//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
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//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
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//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
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//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
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//#define __SYSTEM_CLOCK_84M_PLL_HXTAL (uint32_t)(84000000)
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//#define __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2 (uint32_t)(84000000)
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//#define __SYSTEM_CLOCK_96M_PLL_HXTAL (uint32_t)(96000000)
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//#define __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2 (uint32_t)(96000000)
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//#define __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2 (uint32_t)(96000000)
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#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
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//#define __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2 (uint32_t)(108000000)
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#endif /* GD32F350 */
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#define SEL_IRC8M 0x00
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#define SEL_HXTAL 0x01
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#define SEL_PLL 0x02
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/* set the system clock frequency and declare the system clock configuration function */
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#ifdef __SYSTEM_CLOCK_8M_HXTAL
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
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static void system_clock_8m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
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static void system_clock_72m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
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static void system_clock_72m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2;
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static void system_clock_72m_irc48m(void);
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#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_HXTAL;
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static void system_clock_84m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2;
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static void system_clock_84m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_HXTAL;
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static void system_clock_96m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2;
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static void system_clock_96m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2;
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static void system_clock_96m_irc48m(void);
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#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
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static void system_clock_108m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2;
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static void system_clock_108m_irc8m(void);
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#else
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
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static void system_clock_8m_irc8m(void);
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#endif /* __SYSTEM_CLOCK_8M_HXTAL */
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/* configure the system clock */
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static void system_clock_config(void);
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/*!
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\brief setup the microcontroller system, initialize the system
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\param[in] none
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\param[out] none
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\retval none
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*/
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void SystemInit (void)
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{
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#if (defined(GD32F350))
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RCU_APB2EN = BIT(0);
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CMP_CS |= (CMP_CS_CMP1MSEL | CMP_CS_CMP0MSEL);
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#endif /* GD32F350 */
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/* FPU settings */
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#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* enable IRC8M */
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RCU_CTL0 |= RCU_CTL0_IRC8MEN;
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while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
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}
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/* reset RCU */
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RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
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RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
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RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
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#if (defined(GD32F350))
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RCU_CFG0 &= ~(RCU_CFG0_USBFSPSC);
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RCU_CFG2 &= ~(RCU_CFG2_CECSEL | RCU_CFG2_USBFSPSC2);
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#endif /* GD32F350 */
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RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
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RCU_CFG1 &= ~(RCU_CFG1_PREDV | RCU_CFG1_PLLMF5 | RCU_CFG1_PLLPRESEL);
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RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
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RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
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RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
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RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
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RCU_ADDCTL &= ~RCU_ADDCTL_IRC48MEN;
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RCU_INT = 0x00000000U;
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RCU_ADDINT = 0x00000000U;
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/* configure system clock */
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system_clock_config();
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#ifdef VECT_TAB_SRAM
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nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
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#else
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nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
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#endif
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}
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/*!
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\brief configure the system clock
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_config(void)
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{
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#ifdef __SYSTEM_CLOCK_8M_HXTAL
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system_clock_8m_hxtal();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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system_clock_72m_hxtal();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
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system_clock_72m_irc8m();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
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system_clock_72m_irc48m();
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#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
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system_clock_84m_hxtal();
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#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
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system_clock_84m_irc8m();
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#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
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system_clock_96m_hxtal();
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#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
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system_clock_96m_irc8m();
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#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2)
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system_clock_96m_irc48m();
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#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
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system_clock_108m_hxtal();
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#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
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system_clock_108m_irc8m();
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#else
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system_clock_8m_irc8m();
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#endif /* __SYSTEM_CLOCK_8M_HXTAL */
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}
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#ifdef __SYSTEM_CLOCK_8M_HXTAL
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/*!
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\brief configure the system clock to 8M by HXTAL
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_8m_hxtal(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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/* enable HXTAL */
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RCU_CTL0 |= RCU_CTL0_HXTALEN;
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/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
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}
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while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
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return;
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}
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/* HXTAL is stable */
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
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/* select HXTAL as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
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/* wait until HXTAL is selected as system clock */
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while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){
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}
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}
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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/*!
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\brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_72m_hxtal(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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/* enable HXTAL */
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RCU_CTL0 |= RCU_CTL0_HXTALEN;
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/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
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}
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while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
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return;
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}
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/* HXTAL is stable */
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB/2 */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
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/* APB1 = AHB/2 */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
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/* PLL = HXTAL * 9 = 72 MHz */
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RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
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RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL9);
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/* enable PLL */
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RCU_CTL0 |= RCU_CTL0_PLLEN;
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/* wait until PLL is stable */
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while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
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}
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/* select PLL as system clock */
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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RCU_CFG0 |= RCU_CKSYSSRC_PLL;
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/* wait until PLL is selected as system clock */
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while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
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}
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}
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
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/*!
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\brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
|
||
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\param[in] none
|
||
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\param[out] none
|
||
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\retval none
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||
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*/
|
||
|
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static void system_clock_72m_irc8m(void)
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{
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/* AHB = SYSCLK */
|
||
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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||
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/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
/* PLL = (IRC8M/2) * 18 = 72 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
|
||
|
|
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 72M by PLL which selects IRC48M/2 as its clock source
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_72m_irc48m(void)
|
||
|
|
{
|
||
|
|
/* enable IRC48M */
|
||
|
|
RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN;
|
||
|
|
|
||
|
|
/* wait until IRC48M is stable*/
|
||
|
|
while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)){
|
||
|
|
}
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
/* PLL = (IRC48M/2) * 3 = 96 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
|
||
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
|
||
|
|
RCU_CFG1 |= (RCU_PLL_PREDV2 |RCU_PLLPRESEL_IRC48M);
|
||
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL3);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined (__SYSTEM_CLOCK_84M_PLL_HXTAL)
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 84M by PLL which selects HXTAL as its clock source
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_84m_hxtal(void)
|
||
|
|
{
|
||
|
|
uint32_t timeout = 0U;
|
||
|
|
uint32_t stab_flag = 0U;
|
||
|
|
/* enable HXTAL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_HXTALEN;
|
||
|
|
|
||
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||
|
|
do{
|
||
|
|
timeout++;
|
||
|
|
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
|
||
|
|
}
|
||
|
|
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||
|
|
/* if fail */
|
||
|
|
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
/* HXTAL is stable */
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
|
||
|
|
/* PLL = HXTAL /2 * 21 = 84 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
|
||
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
|
||
|
|
RCU_CFG1 |= RCU_PLL_PREDV2;
|
||
|
|
RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL21);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined (__SYSTEM_CLOCK_84M_PLL_IRC8M_DIV2)
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 84M by PLL which selects IRC8M/2 as its clock source
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_84m_irc8m(void)
|
||
|
|
{
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
/* PLL = (IRC8M/2) * 21 = 84 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
|
||
|
|
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL21);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined (__SYSTEM_CLOCK_96M_PLL_HXTAL)
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 96M by PLL which selects HXTAL as its clock source
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_96m_hxtal(void)
|
||
|
|
{
|
||
|
|
uint32_t timeout = 0U;
|
||
|
|
uint32_t stab_flag = 0U;
|
||
|
|
/* enable HXTAL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_HXTALEN;
|
||
|
|
|
||
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||
|
|
do{
|
||
|
|
timeout++;
|
||
|
|
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
|
||
|
|
}
|
||
|
|
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||
|
|
/* if fail */
|
||
|
|
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
/* HXTAL is stable */
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
|
||
|
|
/* PLL = HXTAL /2 * 24 = 96 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
|
||
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
|
||
|
|
RCU_CFG1 |= RCU_PLL_PREDV2;
|
||
|
|
RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL24);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC8M_DIV2)
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 96M by PLL which selects IRC8M/2 as its clock source
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_96m_irc8m(void)
|
||
|
|
{
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
/* PLL = (IRC8M/2) * 24 = 96 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
|
||
|
|
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL24);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined (__SYSTEM_CLOCK_96M_PLL_IRC48M_DIV2)
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 96M by PLL which selects IRC48M/2 as its clock source
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_96m_irc48m(void)
|
||
|
|
{
|
||
|
|
/* enable IRC48M */
|
||
|
|
RCU_ADDCTL |= RCU_ADDCTL_IRC48MEN;
|
||
|
|
|
||
|
|
/* wait until IRC48M is stable*/
|
||
|
|
while(0U == (RCU_ADDCTL & RCU_ADDCTL_IRC48MSTB)){
|
||
|
|
}
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
/* PLL = (IRC48M/2) * 4 = 96 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
|
||
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
|
||
|
|
RCU_CFG1 |= (RCU_PLL_PREDV2 |RCU_PLLPRESEL_IRC48M);
|
||
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL4);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 84M by PLL which selects HXTAL as its clock source
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_108m_hxtal(void)
|
||
|
|
{
|
||
|
|
uint32_t timeout = 0U;
|
||
|
|
uint32_t stab_flag = 0U;
|
||
|
|
|
||
|
|
/* enable HXTAL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_HXTALEN;
|
||
|
|
|
||
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||
|
|
do{
|
||
|
|
timeout++;
|
||
|
|
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
|
||
|
|
}
|
||
|
|
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||
|
|
/* if fail */
|
||
|
|
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
/* HXTAL is stable */
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
|
||
|
|
/* PLL = HXTAL /2 * 27 = 108 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
|
||
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PLLMF5);
|
||
|
|
RCU_CFG1 |= RCU_PLL_PREDV2;
|
||
|
|
RCU_CFG0 |= (RCU_CFG0_PLLSEL | RCU_PLL_MUL27);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M_DIV2)
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 108M by PLL which selects IRC8M/2 as its clock source
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_108m_irc8m(void)
|
||
|
|
{
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV2;
|
||
|
|
/* APB1 = AHB/2 */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
||
|
|
/* PLL = (IRC8M/2) * 27 = 108 MHz */
|
||
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
|
||
|
|
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27);
|
||
|
|
|
||
|
|
/* enable PLL */
|
||
|
|
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||
|
|
|
||
|
|
/* wait until PLL is stable */
|
||
|
|
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select PLL as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
|
||
|
|
|
||
|
|
/* wait until PLL is selected as system clock */
|
||
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#else
|
||
|
|
/*!
|
||
|
|
\brief configure the system clock to 8M by IRC8M
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
static void system_clock_8m_irc8m(void)
|
||
|
|
{
|
||
|
|
/* AHB = SYSCLK */
|
||
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||
|
|
/* APB2 = AHB */
|
||
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||
|
|
/* APB1 = AHB */
|
||
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||
|
|
|
||
|
|
/* select IRC8M as system clock */
|
||
|
|
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||
|
|
RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
|
||
|
|
|
||
|
|
/* wait until IRC8M is selected as system clock */
|
||
|
|
while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
|
||
|
|
}
|
||
|
|
}
|
||
|
|
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
|
||
|
|
|
||
|
|
/*!
|
||
|
|
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
||
|
|
\param[in] none
|
||
|
|
\param[out] none
|
||
|
|
\retval none
|
||
|
|
*/
|
||
|
|
void SystemCoreClockUpdate (void)
|
||
|
|
{
|
||
|
|
uint32_t sws = 0U;
|
||
|
|
uint32_t pllmf = 0U, pllmf4 = 0U, pllmf5 = 0U, pllsel = 0U, pllpresel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
|
||
|
|
/* exponent of AHB clock divider */
|
||
|
|
const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||
|
|
|
||
|
|
sws = GET_BITS(RCU_CFG0, 2, 3);
|
||
|
|
switch(sws){
|
||
|
|
/* IRC8M is selected as CK_SYS */
|
||
|
|
case SEL_IRC8M:
|
||
|
|
SystemCoreClock = IRC8M_VALUE;
|
||
|
|
break;
|
||
|
|
/* HXTAL is selected as CK_SYS */
|
||
|
|
case SEL_HXTAL:
|
||
|
|
SystemCoreClock = HXTAL_VALUE;
|
||
|
|
break;
|
||
|
|
/* PLL is selected as CK_SYS */
|
||
|
|
case SEL_PLL:
|
||
|
|
/* get the value of PLLMF[3:0] */
|
||
|
|
pllmf = GET_BITS(RCU_CFG0, 18, 21);
|
||
|
|
pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
|
||
|
|
pllmf5 = GET_BITS(RCU_CFG1, 31, 31);
|
||
|
|
/* high 16 bits */
|
||
|
|
if(1U == pllmf4){
|
||
|
|
pllmf += 17U;
|
||
|
|
}else{
|
||
|
|
pllmf += 2U;
|
||
|
|
}
|
||
|
|
if(1U == pllmf5){
|
||
|
|
pllmf += 31U;
|
||
|
|
}
|
||
|
|
/* PLL clock source selection, HXTAL or IRC8M/2 */
|
||
|
|
pllsel = GET_BITS(RCU_CFG0, 16, 16);
|
||
|
|
if(0U != pllsel){
|
||
|
|
prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
|
||
|
|
if(0U == pllpresel){
|
||
|
|
SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
|
||
|
|
}else{
|
||
|
|
SystemCoreClock = (IRC48M_VALUE / prediv) * pllmf;
|
||
|
|
}
|
||
|
|
}else{
|
||
|
|
SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
/* IRC8M is selected as CK_SYS */
|
||
|
|
default:
|
||
|
|
SystemCoreClock = IRC8M_VALUE;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
/* calculate AHB clock frequency */
|
||
|
|
idx = GET_BITS(RCU_CFG0, 4, 7);
|
||
|
|
clk_exp = ahb_exp[idx];
|
||
|
|
SystemCoreClock >>= clk_exp;
|
||
|
|
}
|