500 lines
13 KiB
C
500 lines
13 KiB
C
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/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file ck_aes.c
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* @brief CSI Source File for aes driver
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#include "csi_core.h"
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#include "drv_aes.h"
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#include "ck_aes.h"
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#define ERR_AES(errno) (CSI_DRV_ERRNO_AES_BASE | errno)
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#define AES_NULL_PARA_CHK(para) \
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do { \
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if (para == NULL) { \
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return ERR_AES(EDRV_PARAMETER); \
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} \
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} while (0)
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static ck_aes_reg_t *aes_reg = NULL;
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typedef struct {
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uint32_t base;
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uint32_t irq;
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void *iv;
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uint8_t *result_out;
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uint32_t len;
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aes_event_cb_t cb;
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aes_mode_e mode;
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aes_key_len_bits_e keylen;
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aes_endian_mode_e endian;
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aes_status_t status;
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} ck_aes_priv_t;
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static ck_aes_priv_t aes_handle[CONFIG_AES_NUM];
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/* Driver Capabilities */
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static const aes_capabilities_t driver_capabilities = {
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.ecb_mode = 1, /* ECB mode */
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.cbc_mode = 1, /* CBC mode */
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.cfb_mode = 0, /* CFB mode */
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.ofb_mode = 0, /* OFB mode */
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.ctr_mode = 0, /* CTR mode */
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.bits_128 = 1, /* 128bits key length mode */
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.bits_192 = 1, /* 192bits key lenght mode */
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.bits_256 = 1 /* 256bits key length mode */
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};
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//
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// Functions
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//
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static inline void aes_set_opcode(aes_crypto_mode_e opcode)
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{
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aes_reg->ctrl &= ~(3 << AES_OPCODE_OFFSET); //clear bit[7:6]
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aes_reg->ctrl |= (opcode << AES_OPCODE_OFFSET); //set opcode
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}
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static inline void aes_set_endian(aes_endian_mode_e endian)
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{
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if (endian == AES_ENDIAN_LITTLE) {
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aes_reg->ctrl &= ~AES_LITTLE_ENDIAN;
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} else {
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aes_reg->ctrl |= AES_LITTLE_ENDIAN;
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}
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}
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static inline uint32_t aes_set_keylen(aes_key_len_bits_e keylength)
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{
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aes_reg->ctrl &= ~(3 << AES_KEY_LEN_OFFSET); //clear bit[5:4]
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aes_reg->ctrl |= (keylength << AES_KEY_LEN_OFFSET);// Set key length
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return 0;
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}
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static inline void aes_set_mode(aes_mode_e mode)
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{
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aes_reg->ctrl &= ~(1 << AES_MODE_OFFSET); //clear bit 3
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aes_reg->ctrl |= (mode << AES_MODE_OFFSET); //set mode
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}
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static inline void aes_enable(void)
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{
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aes_reg->ctrl |= (1 << AES_WORK_ENABLE_OFFSET);
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}
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static inline void aes_disable(void)
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{
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aes_reg->ctrl &= ~(1 << AES_WORK_ENABLE_OFFSET);
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}
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static inline void aes_enable_interrupt(void)
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{
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aes_reg->ctrl |= (1 << AES_INT_ENABLE_OFFSET);
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}
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static inline void aes_disable_interrupt(void)
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{
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aes_reg->ctrl &= ~(1 << AES_INT_ENABLE_OFFSET);
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}
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static inline void aes_clear_interrupt(void)
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{
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aes_reg->state = 0x0;
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}
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static inline uint32_t aes_get_intstatus(uint32_t AES_IT)
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{
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return (aes_reg->state & AES_IT) ? 1 : 0;
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}
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static void aes_set_key(void *context, uint8_t *key, uint32_t keylen, uint32_t enc, uint32_t endian)
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{
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uint8_t keynum = 0;
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if (keylen == AES_KEY_LEN_BITS_128) {
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keynum = 4;
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} else if (keylen == AES_KEY_LEN_BITS_192) {
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keynum = 6;
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} else if (keylen == AES_KEY_LEN_BITS_256) {
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keynum = 8;
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}
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uint32_t i;
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/* set key according to the endian mode */
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if (endian == AES_ENDIAN_LITTLE) {
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for (i = 0; i < keynum; i++) {
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aes_reg->key[keynum - 1 - i] = *(uint32_t *)key;
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key += 4;
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}
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} else if (endian == AES_ENDIAN_BIG) {
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for (i = 0; i < keynum; i++) {
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aes_reg->key[i] = *(uint32_t *)key;
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key += 4;
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}
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}
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if (enc == AES_CRYPTO_MODE_DECRYPT) {
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aes_set_opcode(AES_CRYPTO_KEYEXP); /* if the mode is decrypt before decrypt you have to keyexpand */
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aes_enable();
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while (aes_get_intstatus(AES_IT_KEYINT));
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aes_set_opcode(AES_CRYPTO_MODE_DECRYPT);
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} else if (enc == AES_CRYPTO_MODE_ENCRYPT) {
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aes_set_opcode(AES_CRYPTO_MODE_ENCRYPT);
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}
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aes_disable();
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}
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static int aes_crypto(void *context, uint8_t *in, uint8_t *out,
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uint32_t len, uint8_t *iv, uint32_t mode, uint32_t endian)
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{
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uint32_t i = 0;
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/* set iv if the mode is CBC */
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if (mode == AES_MODE_CBC) {
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if (endian == AES_ENDIAN_BIG) {
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for (i = 0; i < 4; i++) {
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aes_reg->iv[i] = *(uint32_t *)iv;
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iv += 4;
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}
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} else if (endian == AES_ENDIAN_LITTLE) {
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for (i = 0; i < 4; i++) {
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aes_reg->iv[3 - i] = *(uint32_t *)iv;
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iv += 4;
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}
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}
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}
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uint32_t j = 0;
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/* set the text before aes calculating */
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for (i = 0; i < len; i = i + 16) {
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for (j = 0; j < 4; j++) {
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if (endian == AES_ENDIAN_BIG) {
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aes_reg->datain[j] = *(uint32_t *)in;
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} else if (endian == AES_ENDIAN_LITTLE) {
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aes_reg->datain[3 - j] = *(uint32_t *)in;
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}
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in += 4;
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}
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aes_enable();
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}
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return 0;
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}
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void ck_aes_irqhandler(int32_t idx)
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{
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ck_aes_priv_t *aes_priv = &aes_handle[idx];
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volatile uint32_t j;
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uint32_t tmp = 0;
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/* get the result after aes calculating*/
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if (aes_priv->result_out != NULL) {
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for (j = 0; j < 4; j++) {
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if (aes_priv->endian == AES_ENDIAN_BIG) {
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tmp = aes_reg->dataout[j];
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} else if (aes_priv->endian == AES_ENDIAN_LITTLE) {
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tmp = aes_reg->dataout[3 - j];
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}
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*(uint32_t *)aes_priv->result_out = tmp;
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aes_priv->result_out += 4;
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aes_priv->len -= 4;
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}
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}
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/* disable aes and clear the aes interrupt */
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aes_disable();
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aes_clear_interrupt();
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/* execute the callback function */
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if (aes_priv->len == 0) {
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if (aes_priv->cb) {
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aes_priv->cb(AES_EVENT_CRYPTO_COMPLETE);
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}
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}
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}
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int32_t __attribute__((weak)) target_get_aes_count(void)
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{
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return 0;
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}
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int32_t __attribute__((weak)) target_get_aes(int32_t idx, uint32_t *base, uint32_t *irq)
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{
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return NULL;
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}
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/**
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\brief get aes instance count.
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\return aes handle count
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*/
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int32_t csi_aes_get_instance_count(void)
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{
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return target_get_aes_count();
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}
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/**
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\brief Initialize AES Interface. 1. Initializes the resources needed for the AES interface 2.registers event callback function
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\param[in] idx must not exceed return value of csi_aes_get_instance_count().
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\param[in] cb_event Pointer to \ref aes_event_cb_t
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\return return aes handle if success
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*/
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aes_handle_t csi_aes_initialize(int32_t idx, aes_event_cb_t cb_event)
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{
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if (idx < 0 || idx >= CONFIG_AES_NUM) {
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return NULL;
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}
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uint32_t irq = 0u;
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uint32_t base = 0u;
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/* obtain the aes information */
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int32_t real_idx = target_get_aes(idx, &base, &irq);
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if (real_idx != idx) {
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return NULL;
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}
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ck_aes_priv_t *aes_priv = &aes_handle[idx];
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aes_priv->base = base;
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aes_priv->irq = irq;
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/* initialize the aes context */
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aes_reg = (ck_aes_reg_t *)(aes_priv->base);
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aes_priv->cb = cb_event;
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aes_priv->iv = NULL;
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aes_priv->len = 16;
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aes_priv->result_out = NULL;
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aes_priv->mode = AES_MODE_CBC;
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aes_priv->keylen = AES_KEY_LEN_BITS_128;
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aes_priv->endian = AES_ENDIAN_LITTLE;
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aes_priv->status.busy = 0;
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aes_enable_interrupt(); /* enable the aes interrupt */
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drv_nvic_enable_irq(aes_priv->irq); /* enable the aes bit in nvic */
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return (aes_handle_t)aes_priv;
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}
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/**
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\brief De-initialize AES Interface. stops operation and releases the software resources used by the interface
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\param[in] handle aes handle to operate.
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\return error code
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*/
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int32_t csi_aes_uninitialize(aes_handle_t handle)
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{
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AES_NULL_PARA_CHK(handle);
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ck_aes_priv_t *aes_priv = handle;
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aes_priv->cb = NULL;
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aes_disable_interrupt(); /* disable the aes interrupt */
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drv_nvic_disable_irq(aes_priv->irq);
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return 0;
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}
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/**
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\brief Get driver capabilities.
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\param[in] handle aes handle to operate.
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\return \ref aes_capabilities_t
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*/
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aes_capabilities_t csi_aes_get_capabilities(aes_handle_t handle)
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{
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return driver_capabilities;
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}
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/**
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\brief config aes mode.
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\param[in] handle aes handle to operate.
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\param[in] mode \ref aes_mode_e
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\param[in] keylen_bits \ref aes_key_len_bits_e
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\param[in] endian \ref aes_endian_mode_e
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\param[in] arg Pointer to the iv address when mode is cbc_mode
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\return error code
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*/
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int32_t csi_aes_config(aes_handle_t handle, aes_mode_e mode, aes_key_len_bits_e keylen_bits, aes_endian_mode_e endian, uint32_t arg)
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{
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AES_NULL_PARA_CHK(handle);
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ck_aes_priv_t *aes_priv = handle;
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aes_reg = (ck_aes_reg_t *)(aes_priv->base);
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/* config the aes mode */
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switch (mode) {
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case AES_MODE_CBC:
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aes_priv->iv = (void *)arg;
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aes_priv->mode = mode;
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aes_set_mode(mode);
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break;
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case AES_MODE_ECB:
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aes_priv->mode = mode;
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aes_set_mode(mode);
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break;
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case AES_MODE_CFB:
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case AES_MODE_OFB:
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case AES_MODE_CTR:
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return ERR_AES(EDRV_UNSUPPORTED);
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default:
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return ERR_AES(EDRV_PARAMETER);
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}
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/* config the key length */
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switch (keylen_bits) {
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case AES_KEY_LEN_BITS_128:
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case AES_KEY_LEN_BITS_192:
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case AES_KEY_LEN_BITS_256:
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aes_priv->keylen = keylen_bits;
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aes_set_keylen(keylen_bits);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return ERR_AES(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* config the endian mode */
|
||
|
|
switch (endian) {
|
||
|
|
case AES_ENDIAN_LITTLE:
|
||
|
|
aes_priv->endian = endian;
|
||
|
|
aes_set_endian(endian);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case AES_ENDIAN_BIG:
|
||
|
|
aes_priv->endian = endian;
|
||
|
|
aes_set_endian(endian);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return ERR_AES(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief set crypto key.
|
||
|
|
\param[in] handle aes handle to operate.
|
||
|
|
\param[in] context aes information context(NULL when hardware implementation)
|
||
|
|
\param[in] key Pointer to the key buf
|
||
|
|
\param[in] key_len the key len
|
||
|
|
\param[in] enc \ref aes_crypto_mode_e
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_aes_set_key(aes_handle_t handle, void *context, void *key, uint32_t key_len, aes_crypto_mode_e enc)
|
||
|
|
{
|
||
|
|
AES_NULL_PARA_CHK(handle);
|
||
|
|
AES_NULL_PARA_CHK(key);
|
||
|
|
if ((key_len != AES_KEY_LEN_BITS_128 &&
|
||
|
|
key_len != AES_KEY_LEN_BITS_192 &&
|
||
|
|
key_len != AES_KEY_LEN_BITS_256) ||
|
||
|
|
(enc != AES_CRYPTO_MODE_ENCRYPT &&
|
||
|
|
enc != AES_CRYPTO_MODE_DECRYPT)) {
|
||
|
|
return ERR_AES(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
ck_aes_priv_t *aes_priv = handle;
|
||
|
|
aes_set_key(context, key, key_len, enc, aes_priv->endian);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief encrypt or decrypt
|
||
|
|
\param[in] handle aes handle to operate.
|
||
|
|
\param[in] context aes information context(NULL when hardware implementation)
|
||
|
|
\param[in] in Pointer to the Source data
|
||
|
|
\param[out] out Pointer to the Result data.
|
||
|
|
\param[in] len the Source data len.
|
||
|
|
\param[in] padding \ref aes_padding_mode_e.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_aes_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, aes_padding_mode_e padding)
|
||
|
|
{
|
||
|
|
AES_NULL_PARA_CHK(handle);
|
||
|
|
AES_NULL_PARA_CHK(in);
|
||
|
|
AES_NULL_PARA_CHK(out);
|
||
|
|
AES_NULL_PARA_CHK(len);
|
||
|
|
|
||
|
|
ck_aes_priv_t *aes_priv = handle;
|
||
|
|
|
||
|
|
aes_priv->status.busy = 1;
|
||
|
|
|
||
|
|
uint8_t left_len = len & 0xf;
|
||
|
|
switch (padding) {
|
||
|
|
case AES_PADDING_MODE_NO:
|
||
|
|
if (left_len) {
|
||
|
|
return ERR_AES(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* crypto in padding no mode */
|
||
|
|
aes_priv->result_out = out;
|
||
|
|
aes_priv->len = len;
|
||
|
|
aes_crypto(context, in, out, len, aes_priv->iv, aes_priv->mode, aes_priv->endian);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case AES_PADDING_MODE_ZERO:
|
||
|
|
if (left_len == 0) {
|
||
|
|
return ERR_AES(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
uint8_t i = 0;
|
||
|
|
for (i = 0; i < (16 - left_len); i++) {
|
||
|
|
*((uint8_t *)in + len + i) = 0x0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* crypto in padding zero mode */
|
||
|
|
aes_priv->result_out = out;
|
||
|
|
aes_priv->len = len + 16 -left_len;
|
||
|
|
aes_crypto(context, in, out, len + 16 - left_len, aes_priv->iv, aes_priv->mode, aes_priv->endian);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case AES_PADDING_MODE_PKCS5:
|
||
|
|
return ERR_AES(EDRV_UNSUPPORTED);
|
||
|
|
|
||
|
|
default:
|
||
|
|
return ERR_AES(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
aes_priv->status.busy = 0;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Get AES status.
|
||
|
|
\param[in] handle aes handle to operate.
|
||
|
|
\return AES status \ref aes_status_t
|
||
|
|
*/
|
||
|
|
aes_status_t csi_aes_get_status(aes_handle_t handle)
|
||
|
|
{
|
||
|
|
ck_aes_priv_t *aes_priv = handle;
|
||
|
|
return aes_priv->status;
|
||
|
|
}
|