2018-12-25 15:59:44 +08:00
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-19 zylx first version
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*/
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#include "board.h"
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#ifdef BSP_USING_EXT_FMC_IO
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//#define DRV_DEBUG
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#define LOG_TAG "drv.ext_io"
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#include <drv_log.h>
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#include "drv_ext_io.h"
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#define HC574_PORT *(volatile rt_uint32_t *)0x64001000
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volatile rt_uint32_t HC574_state = 0;
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2018-12-28 16:29:42 +08:00
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void HC574_SetPin(rt_uint32_t _pin, uint8_t _value)
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2018-12-25 15:59:44 +08:00
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{
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if (_value == 0)
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{
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HC574_state &= (~_pin);
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}
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else
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{
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HC574_state |= _pin;
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}
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HC574_PORT = HC574_state;
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}
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rt_uint8_t HC574_GetPin(rt_uint32_t _pin)
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{
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if (HC574_state & _pin)
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{
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return 1;
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}
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else
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{
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return 0;
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}
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}
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static void HC574_Config_FMC(void)
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{
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FMC_NORSRAM_TimingTypeDef timing = {0};
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SRAM_HandleTypeDef sram2 = {0};
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/*
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For LCD compatibility<EFBFBD><EFBFBD>select 3-0-6-1-0-0
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3-0-5-1-0-0 : RD high level 75ns<EFBFBD><EFBFBD>low level 50ns. Read 8 channels of data into memory in 1us.
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1-0-1-1-0-0 : RD high level 75ns<EFBFBD><EFBFBD>low level 12ns<EFBFBD><EFBFBD>trailing edge 12ns.
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*/
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/* FMC_Bank1_NORSRAM2 configuration */
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timing.AddressSetupTime = 3;
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timing.AddressHoldTime = 0;
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timing.DataSetupTime = 6;
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timing.BusTurnAroundDuration = 1;
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timing.CLKDivision = 0;
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timing.DataLatency = 0;
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timing.AccessMode = FMC_ACCESS_MODE_A;
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/*
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LCD configured as follow:
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- Data/Address MUX = Disable
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- Memory Type = SRAM
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- Data Width = 32bit
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- Write Operation = Enable
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- Extended Mode = Enable
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- Asynchronous Wait = Disable
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*/
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sram2.Instance = FMC_NORSRAM_DEVICE;
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sram2.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
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sram2.Init.NSBank = FMC_NORSRAM_BANK2;
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sram2.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
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sram2.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
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sram2.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
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sram2.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
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sram2.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
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sram2.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
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sram2.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
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sram2.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
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sram2.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
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sram2.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
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sram2.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
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sram2.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
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sram2.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
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sram2.Init.PageSize = FMC_PAGE_SIZE_1024;
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if (HAL_SRAM_Init(&sram2, &timing, NULL) != HAL_OK)
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{
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LOG_E("extend IO init failed!");
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}
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else
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{
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LOG_D("extend IO init success");
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}
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}
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static int stm32_ext_io_init(void)
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{
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HC574_Config_FMC();
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/* Set the chip select to high level */
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HC574_state = (NRF24L01_CE | VS1053_XDCS | LED1 | LED2 | LED3 | LED4 );
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/* Change IO state */
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HC574_PORT = HC574_state;
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return RT_EOK;
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}
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INIT_BOARD_EXPORT(stm32_ext_io_init);
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#endif /* BSP_USING_EXT_FMC_IO */
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