2021-09-02 09:55:07 +08:00
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/*
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2023-03-20 12:04:18 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2021-09-02 09:55:07 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 Abbcc first version
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2023-01-05 14:15:02 +08:00
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* 2022-12-26 luobeihai add apm32F0 serie MCU support
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2021-09-02 09:55:07 +08:00
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*/
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#include "board.h"
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#include "drv_usart.h"
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#ifdef RT_USING_SERIAL
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2023-01-05 14:15:02 +08:00
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#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && \
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!defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \
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!defined(BSP_USING_UART5) && !defined(BSP_USING_UART6)
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2021-09-05 21:40:55 +08:00
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#error "Please define at least one BSP_USING_UARTx"
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/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
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2021-09-02 09:55:07 +08:00
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#endif
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struct apm32_usart
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{
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const char *name;
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USART_T *usartx;
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IRQn_Type irq_type;
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struct rt_serial_device serial;
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};
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enum
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{
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#ifdef BSP_USING_UART1
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UART1_INDEX,
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#endif
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#ifdef BSP_USING_UART2
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UART2_INDEX,
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#endif
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2023-01-05 14:15:02 +08:00
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#ifdef BSP_USING_UART3
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UART3_INDEX,
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#endif
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#ifdef BSP_USING_UART4
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UART4_INDEX,
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#endif
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#ifdef BSP_USING_UART5
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UART5_INDEX,
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#endif
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#ifdef BSP_USING_UART6
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UART6_INDEX,
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#endif
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2021-09-02 09:55:07 +08:00
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};
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static struct apm32_usart usart_config[] =
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{
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#ifdef BSP_USING_UART1
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2021-09-05 21:40:55 +08:00
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{
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"uart1",
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2021-09-02 09:55:07 +08:00
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USART1,
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2021-09-05 21:40:55 +08:00
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USART1_IRQn,
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},
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2021-09-02 09:55:07 +08:00
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#endif
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#ifdef BSP_USING_UART2
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2021-09-05 21:40:55 +08:00
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{
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"uart2",
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2021-09-02 09:55:07 +08:00
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USART2,
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2021-09-05 21:40:55 +08:00
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USART2_IRQn,
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},
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2021-09-02 09:55:07 +08:00
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#endif
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F1) || defined(SOC_SERIES_APM32F4)
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#ifdef BSP_USING_UART3
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{
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"uart3",
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USART3,
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USART3_IRQn,
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},
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#endif
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#ifdef BSP_USING_UART4
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{
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"uart4",
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UART4,
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UART4_IRQn,
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},
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#endif
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#ifdef BSP_USING_UART5
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{
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"uart5",
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UART5,
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UART5_IRQn,
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},
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#endif
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#ifdef BSP_USING_UART6
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{
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"uart6",
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USART6,
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USART6_IRQn,
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},
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#endif
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#endif
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2021-09-02 09:55:07 +08:00
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};
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2023-01-05 14:15:02 +08:00
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static rt_err_t apm32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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2021-09-02 09:55:07 +08:00
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{
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USART_Config_T USART_ConfigStruct;
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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struct apm32_usart *usart_instance = (struct apm32_usart *) serial->parent.user_data;
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apm32_usart_init();
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2021-09-05 21:40:55 +08:00
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2023-01-05 14:15:02 +08:00
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USART_ConfigStruct.baudRate = cfg->baud_rate;
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2021-09-02 09:55:07 +08:00
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USART_ConfigStruct.mode = USART_MODE_TX_RX;
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USART_ConfigStruct.parity = USART_PARITY_NONE;
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2023-03-20 12:04:18 +08:00
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F0)
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switch (cfg->flowcontrol)
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{
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case RT_SERIAL_FLOWCONTROL_NONE:
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USART_ConfigStruct.hardwareFlowCtrl = USART_FLOW_CTRL_NONE;
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break;
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case RT_SERIAL_FLOWCONTROL_CTSRTS:
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USART_ConfigStruct.hardwareFlowCtrl = USART_FLOW_CTRL_RTS_CTS;
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break;
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default:
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USART_ConfigStruct.hardwareFlowCtrl = USART_FLOW_CTRL_NONE;
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break;
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}
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#else
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switch (cfg->flowcontrol)
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{
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case RT_SERIAL_FLOWCONTROL_NONE:
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USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_NONE;
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break;
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case RT_SERIAL_FLOWCONTROL_CTSRTS:
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USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_RTS_CTS;
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break;
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default:
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USART_ConfigStruct.hardwareFlow = USART_HARDWARE_FLOW_NONE;
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break;
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}
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#endif
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2021-09-02 09:55:07 +08:00
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switch (cfg->data_bits)
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{
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case DATA_BITS_8:
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if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN)
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USART_ConfigStruct.wordLength = USART_WORD_LEN_9B;
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else
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USART_ConfigStruct.wordLength = USART_WORD_LEN_8B;
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break;
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case DATA_BITS_9:
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USART_ConfigStruct.wordLength = USART_WORD_LEN_9B;
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break;
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default:
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USART_ConfigStruct.wordLength = USART_WORD_LEN_8B;
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break;
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}
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switch (cfg->stop_bits)
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{
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case STOP_BITS_1:
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USART_ConfigStruct.stopBits = USART_STOP_BIT_1;
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break;
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case STOP_BITS_2:
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USART_ConfigStruct.stopBits = USART_STOP_BIT_2;
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break;
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default:
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USART_ConfigStruct.stopBits = USART_STOP_BIT_1;
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break;
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}
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switch (cfg->parity)
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{
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case PARITY_NONE:
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USART_ConfigStruct.parity = USART_PARITY_NONE;
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break;
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case PARITY_ODD:
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USART_ConfigStruct.parity = USART_PARITY_ODD;
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break;
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case PARITY_EVEN:
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USART_ConfigStruct.parity = USART_PARITY_EVEN;
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break;
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default:
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USART_ConfigStruct.parity = USART_PARITY_NONE;
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break;
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}
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USART_Config(usart_instance->usartx, &USART_ConfigStruct);
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USART_Enable(usart_instance->usartx);
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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return RT_EOK;
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}
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2023-01-05 14:15:02 +08:00
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static rt_err_t apm32_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
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2021-09-02 09:55:07 +08:00
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{
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struct apm32_usart *usart;
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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RT_ASSERT(serial != RT_NULL);
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usart = (struct apm32_usart *) serial->parent.user_data;
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RT_ASSERT(usart != RT_NULL);
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F0)
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switch (cmd)
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{
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/* disable interrupt */
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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NVIC_DisableIRQRequest(usart->irq_type);
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/* disable interrupt */
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USART_DisableInterrupt(usart->usartx, USART_INT_RXBNEIE);
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break;
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/* enable interrupt */
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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NVIC_EnableIRQRequest(usart->irq_type, 1);
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/* enable interrupt */
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USART_EnableInterrupt(usart->usartx, USART_INT_RXBNEIE);
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break;
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}
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#else
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2021-09-02 09:55:07 +08:00
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switch (cmd)
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{
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/* disable interrupt */
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case RT_DEVICE_CTRL_CLR_INT:
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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/* disable rx irq */
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NVIC_DisableIRQRequest(usart->irq_type);
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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/* disable interrupt */
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USART_DisableInterrupt(usart->usartx, USART_INT_RXBNE);
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break;
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/* enable interrupt */
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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NVIC_EnableIRQRequest(usart->irq_type, 1, 0);
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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/* enable interrupt */
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USART_EnableInterrupt(usart->usartx, USART_INT_RXBNE);
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break;
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}
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2023-01-05 14:15:02 +08:00
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#endif
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2021-09-02 09:55:07 +08:00
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return RT_EOK;
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}
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2023-01-05 14:15:02 +08:00
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static int apm32_uart_putc(struct rt_serial_device *serial, char c)
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2021-09-02 09:55:07 +08:00
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{
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struct apm32_usart *usart;
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RT_ASSERT(serial != RT_NULL);
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usart = (struct apm32_usart *) serial->parent.user_data;
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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RT_ASSERT(usart != RT_NULL);
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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USART_TxData(usart->usartx, (uint8_t) c);
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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while (USART_ReadStatusFlag(usart->usartx, USART_FLAG_TXC) == RESET);
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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return 1;
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}
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2023-01-05 14:15:02 +08:00
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static int apm32_uart_getc(struct rt_serial_device *serial)
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2021-09-02 09:55:07 +08:00
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{
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int ch;
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struct apm32_usart *usart;
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RT_ASSERT(serial != RT_NULL);
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usart = (struct apm32_usart *) serial->parent.user_data;
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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RT_ASSERT(usart != RT_NULL);
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ch = -1;
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if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET)
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{
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ch = USART_RxData(usart->usartx);
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}
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return ch;
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}
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/**
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* Uart common interrupt process. This need add to usart ISR.
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*
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* @param serial serial device
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*/
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static void usart_isr(struct rt_serial_device *serial)
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{
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struct apm32_usart *usart;
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RT_ASSERT(serial != RT_NULL);
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usart = (struct apm32_usart *) serial->parent.user_data;
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2021-09-05 21:40:55 +08:00
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2021-09-02 09:55:07 +08:00
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RT_ASSERT(usart != RT_NULL);
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2022-03-08 12:03:06 +08:00
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/* UART in mode Receiver */
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F0)
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if ((USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) &&
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(USART_ReadIntFlag(usart->usartx, USART_INT_FLAG_RXBNE) != RESET))
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#else
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2021-09-02 09:55:07 +08:00
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if ((USART_ReadStatusFlag(usart->usartx, USART_FLAG_RXBNE) != RESET) &&
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(USART_ReadIntFlag(usart->usartx, USART_INT_RXBNE) != RESET))
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2023-01-05 14:15:02 +08:00
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#endif
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2021-09-02 09:55:07 +08:00
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{
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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}
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else
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{
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2023-01-05 14:15:02 +08:00
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#if defined(SOC_SERIES_APM32F0)
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if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_OVRE) != RESET)
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{
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USART_ClearStatusFlag(usart->usartx, USART_FLAG_OVRE);
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}
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if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_NEF) != RESET)
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{
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USART_ClearStatusFlag(usart->usartx, USART_FLAG_NEF);
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}
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if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_FEF) != RESET)
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{
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USART_ClearStatusFlag(usart->usartx, USART_FLAG_FEF);
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}
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if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_PEF) != RESET)
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{
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USART_ClearStatusFlag(usart->usartx, USART_FLAG_PEF);
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}
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if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_CTSF) != RESET)
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|
|
{
|
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_CTSF);
|
|
|
|
}
|
|
|
|
if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_LBDF) != RESET)
|
|
|
|
{
|
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_LBDF);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_OVRE) != RESET)
|
|
|
|
{
|
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_OVRE);
|
|
|
|
}
|
|
|
|
if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_NE) != RESET)
|
|
|
|
{
|
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_NE);
|
|
|
|
}
|
|
|
|
if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_FE) != RESET)
|
|
|
|
{
|
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_FE);
|
|
|
|
}
|
|
|
|
if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_PE) != RESET)
|
|
|
|
{
|
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_PE);
|
|
|
|
}
|
2021-09-05 21:40:55 +08:00
|
|
|
if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_CTS) != RESET)
|
|
|
|
{
|
2021-09-02 09:55:07 +08:00
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_CTS);
|
|
|
|
}
|
2021-09-05 21:40:55 +08:00
|
|
|
if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_LBD) != RESET)
|
|
|
|
{
|
2021-09-02 09:55:07 +08:00
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_LBD);
|
|
|
|
}
|
2023-01-05 14:15:02 +08:00
|
|
|
#endif
|
2021-09-05 21:40:55 +08:00
|
|
|
if (USART_ReadStatusFlag(usart->usartx, USART_FLAG_TXBE) != RESET)
|
|
|
|
{
|
2021-09-02 09:55:07 +08:00
|
|
|
USART_ClearStatusFlag(usart->usartx, USART_FLAG_TXBE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART1)
|
|
|
|
void USART1_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
usart_isr(&(usart_config[UART1_INDEX].serial));
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* BSP_USING_UART1 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART2)
|
|
|
|
void USART2_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
usart_isr(&(usart_config[UART2_INDEX].serial));
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART2 */
|
|
|
|
|
2023-01-05 14:15:02 +08:00
|
|
|
#if defined(BSP_USING_UART3)
|
|
|
|
void USART3_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
usart_isr(&(usart_config[UART3_INDEX].serial));
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART3 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART4)
|
|
|
|
void UART4_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
usart_isr(&(usart_config[UART4_INDEX].serial));
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART4 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART5)
|
|
|
|
void UART5_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
usart_isr(&(usart_config[UART5_INDEX].serial));
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART5 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART6)
|
|
|
|
void USART6_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
usart_isr(&(usart_config[UART6_INDEX].serial));
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART6 */
|
|
|
|
|
2021-09-02 09:55:07 +08:00
|
|
|
static const struct rt_uart_ops apm32_usart_ops =
|
|
|
|
{
|
2023-01-05 14:15:02 +08:00
|
|
|
.configure = apm32_uart_configure,
|
|
|
|
.control = apm32_uart_control,
|
|
|
|
.putc = apm32_uart_putc,
|
|
|
|
.getc = apm32_uart_getc,
|
2021-09-02 09:55:07 +08:00
|
|
|
.dma_transmit = RT_NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
int rt_hw_usart_init(void)
|
|
|
|
{
|
|
|
|
rt_size_t obj_num;
|
|
|
|
int index;
|
|
|
|
|
|
|
|
obj_num = sizeof(usart_config) / sizeof(struct apm32_usart);
|
|
|
|
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
|
|
|
rt_err_t result = 0;
|
|
|
|
|
2021-09-05 21:40:55 +08:00
|
|
|
for (index = 0; index < obj_num; index++)
|
|
|
|
{
|
2021-09-02 09:55:07 +08:00
|
|
|
usart_config[index].serial.ops = &apm32_usart_ops;
|
|
|
|
usart_config[index].serial.config = config;
|
|
|
|
|
|
|
|
/* register USART device */
|
|
|
|
result = rt_hw_serial_register(&usart_config[index].serial,
|
2021-09-05 21:40:55 +08:00
|
|
|
usart_config[index].name,
|
|
|
|
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
|
|
|
|
| RT_DEVICE_FLAG_INT_TX, &usart_config[index]);
|
2021-09-02 09:55:07 +08:00
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* RT_USING_SERIAL */
|