348 lines
10 KiB
C
348 lines
10 KiB
C
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/*
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* File : drv_spi.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2017-06-05 tanek first implementation.
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*/
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#include "drv_spi.h"
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#include <board.h>
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#include <finsh.h>
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//#define DEBUG
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#define ARR_LEN(__N) (sizeof(__N) / sizeof(__N[0]))
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#ifdef DEBUG
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#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
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#else
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#define DEBUG_PRINTF(...)
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#endif
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/* private rt-thread spi ops function */
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message);
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static struct rt_spi_ops stm32_spi_ops =
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{
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configure,
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xfer
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};
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static rt_err_t configure(struct rt_spi_device* device,
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struct rt_spi_configuration* configuration)
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{
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struct rt_spi_bus * spi_bus = (struct rt_spi_bus *)device->bus;
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struct stm32f4_spi *f4_spi = (struct stm32f4_spi *)spi_bus->parent.user_data;
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spi_parameter_struct spi_init_struct;
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uint32_t spi_periph = f4_spi->spi_periph;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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/* data_width */
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if(configuration->data_width <= 8)
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{
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spi_init_struct.frame_size = SPI_FRAMESIZE_8BIT;
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}
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else if(configuration->data_width <= 16)
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{
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spi_init_struct.frame_size = SPI_FRAMESIZE_16BIT;
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}
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else
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{
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return RT_EIO;
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}
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/* baudrate */
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{
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rcu_clock_freq_enum spi_src;
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uint32_t spi_apb_clock;
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uint32_t max_hz;
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max_hz = configuration->max_hz;
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DEBUG_PRINTF("sys freq: %d\n", HAL_RCC_GetSysClockFreq());
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DEBUG_PRINTF("pclk2 freq: %d\n", HAL_RCC_GetPCLK2Freq());
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DEBUG_PRINTF("max freq: %d\n", max_hz);
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if (spi_periph == SPI1 || spi_periph == SPI2)
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{
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spi_src = CK_APB1;
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}
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else
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{
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spi_src = CK_APB2;
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}
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spi_apb_clock = rcu_clock_freq_get(spi_src);
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if(max_hz >= spi_apb_clock/2)
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{
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spi_init_struct.prescale = SPI_PSC_2;
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}
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else if (max_hz >= spi_apb_clock/4)
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{
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spi_init_struct.prescale = SPI_PSC_4;
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}
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else if (max_hz >= spi_apb_clock/8)
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{
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spi_init_struct.prescale = SPI_PSC_8;
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}
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else if (max_hz >= spi_apb_clock/16)
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{
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spi_init_struct.prescale = SPI_PSC_16;
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}
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else if (max_hz >= spi_apb_clock/32)
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{
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spi_init_struct.prescale = SPI_PSC_32;
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}
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else if (max_hz >= spi_apb_clock/64)
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{
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spi_init_struct.prescale = SPI_PSC_64;
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}
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else if (max_hz >= spi_apb_clock/128)
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{
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spi_init_struct.prescale = SPI_PSC_128;
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}
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else
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{
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/* min prescaler 256 */
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spi_init_struct.prescale = SPI_PSC_256;
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}
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} /* baudrate */
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switch(configuration->mode)
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{
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case RT_SPI_MODE_0:
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spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
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break;
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case RT_SPI_MODE_1:
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spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_2EDGE;
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break;
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case RT_SPI_MODE_2:
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spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_1EDGE;
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break;
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case RT_SPI_MODE_3:
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spi_init_struct.clock_polarity_phase = SPI_CK_PL_HIGH_PH_2EDGE;
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break;
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}
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/* MSB or LSB */
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if(configuration->mode & RT_SPI_MSB)
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{
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spi_init_struct.endian = SPI_ENDIAN_MSB;
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}
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else
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{
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spi_init_struct.endian = SPI_ENDIAN_LSB;
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}
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spi_init_struct.trans_mode = SPI_TRANSMODE_FULLDUPLEX;
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spi_init_struct.device_mode = SPI_MASTER;
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spi_init_struct.nss = SPI_NSS_SOFT;
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spi_crc_off(spi_periph);
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/* init SPI */
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spi_init(spi_periph, &spi_init_struct);
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/* Enable SPI_MASTER */
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spi_enable(spi_periph);
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return RT_EOK;
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};
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static rt_uint32_t xfer(struct rt_spi_device* device, struct rt_spi_message* message)
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{
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struct rt_spi_bus * stm32_spi_bus = (struct rt_spi_bus *)device->bus;
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struct stm32f4_spi *f4_spi = (struct stm32f4_spi *)stm32_spi_bus->parent.user_data;
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struct rt_spi_configuration * config = &device->config;
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struct stm32_spi_cs * stm32_spi_cs = device->parent.user_data;
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uint32_t spi_periph = f4_spi->spi_periph;
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RT_ASSERT(device != NULL);
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RT_ASSERT(message != NULL);
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/* take CS */
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if(message->cs_take)
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{
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gpio_bit_reset(stm32_spi_cs->GPIOx, stm32_spi_cs->GPIO_Pin);
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DEBUG_PRINTF("spi take cs\n");
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}
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{
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if(config->data_width <= 8)
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{
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const rt_uint8_t * send_ptr = message->send_buf;
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rt_uint8_t * recv_ptr = message->recv_buf;
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rt_uint32_t size = message->length;
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DEBUG_PRINTF("spi poll transfer start: %d\n", size);
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while(size--)
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{
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rt_uint8_t data = 0xFF;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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// Todo: replace register read/write by stm32f4 lib
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//Wait until the transmit buffer is empty
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while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
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// Send the byte
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spi_i2s_data_transmit(spi_periph, data);
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//Wait until a data is received
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while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
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// Get the received data
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data = spi_i2s_data_receive(spi_periph);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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DEBUG_PRINTF("spi poll transfer finsh\n");
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}
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else if(config->data_width <= 16)
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{
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const rt_uint16_t * send_ptr = message->send_buf;
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rt_uint16_t * recv_ptr = message->recv_buf;
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rt_uint32_t size = message->length;
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while(size--)
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{
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rt_uint16_t data = 0xFF;
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if(send_ptr != RT_NULL)
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{
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data = *send_ptr++;
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}
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//Wait until the transmit buffer is empty
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while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_TBE));
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// Send the byte
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spi_i2s_data_transmit(spi_periph, data);
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//Wait until a data is received
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while(RESET == spi_i2s_flag_get(spi_periph, SPI_FLAG_RBNE));
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// Get the received data
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data = spi_i2s_data_receive(spi_periph);
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if(recv_ptr != RT_NULL)
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{
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*recv_ptr++ = data;
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}
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}
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}
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}
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/* release CS */
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if(message->cs_release)
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{
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gpio_bit_set(stm32_spi_cs->GPIOx, stm32_spi_cs->GPIO_Pin);
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DEBUG_PRINTF("spi release cs\n");
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}
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return message->length;
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};
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static struct rt_spi_bus spi_bus[];
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static const struct stm32f4_spi spis[] = {
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#ifdef RT_USING_SPI0
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{SPI0, RCU_SPI0, &spi_bus[0]},
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#endif
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#ifdef RT_USING_SPI1
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{SPI1, RCU_SPI1, &spi_bus[1]},
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#endif
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#ifdef RT_USING_SPI2
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{SPI2, RCU_SPI2, &spi_bus[2]},
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#endif
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#ifdef RT_USING_SPI3
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{SPI3, RCU_SPI3, &spi_bus[3]},
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#endif
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#ifdef RT_USING_SPI4
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{SPI4, RCU_SPI4, &spi_bus[4]},
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#endif
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#ifdef RT_USING_SPI5
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{SPI5, RCU_SPI5, &spi_bus[5]},
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#endif
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};
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static struct rt_spi_bus spi_bus[ARR_LEN(spis)];
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/** \brief init and register stm32 spi bus.
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*
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* \param SPI: STM32 SPI, e.g: SPI1,SPI2,SPI3.
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* \param spi_bus_name: spi bus name, e.g: "spi1"
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* \return
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*
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*/
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rt_err_t stm32_spi_bus_register(uint32_t spi_periph,
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//struct stm32_spi_bus * stm32_spi,
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const char * spi_bus_name)
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{
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int i;
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RT_ASSERT(spi_bus_name != RT_NULL);
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for (i = 0; i < ARR_LEN(spis); i++)
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{
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if (spi_periph == spis[i].spi_periph)
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{
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rcu_periph_clock_enable(spis[i].spi_clk);
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spis[i].spi_bus->parent.user_data = (void *)&spis[i];
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rt_spi_bus_register(spis[i].spi_bus, spi_bus_name, &stm32_spi_ops);
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return RT_EOK;
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}
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}
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return RT_ERROR;
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#ifdef SPI_USE_DMA
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/* Configure the DMA handler for Transmission process */
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p_spi_bus->hdma_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
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p_spi_bus->hdma_tx.Init.PeriphInc = DMA_PINC_DISABLE;
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//p_spi_bus->hdma_tx.Init.MemInc = DMA_MINC_ENABLE;
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p_spi_bus->hdma_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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p_spi_bus->hdma_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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p_spi_bus->hdma_tx.Init.Mode = DMA_NORMAL;
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p_spi_bus->hdma_tx.Init.Priority = DMA_PRIORITY_LOW;
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p_spi_bus->hdma_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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p_spi_bus->hdma_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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p_spi_bus->hdma_tx.Init.MemBurst = DMA_MBURST_INC4;
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p_spi_bus->hdma_tx.Init.PeriphBurst = DMA_PBURST_INC4;
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p_spi_bus->hdma_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
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p_spi_bus->hdma_rx.Init.PeriphInc = DMA_PINC_DISABLE;
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//p_spi_bus->hdma_rx.Init.MemInc = DMA_MINC_ENABLE;
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p_spi_bus->hdma_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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p_spi_bus->hdma_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
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p_spi_bus->hdma_rx.Init.Mode = DMA_NORMAL;
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p_spi_bus->hdma_rx.Init.Priority = DMA_PRIORITY_HIGH;
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p_spi_bus->hdma_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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p_spi_bus->hdma_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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p_spi_bus->hdma_rx.Init.MemBurst = DMA_MBURST_INC4;
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p_spi_bus->hdma_rx.Init.PeriphBurst = DMA_PBURST_INC4;
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#endif
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}
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