2016-04-24 19:34:41 +08:00
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/*
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2019-07-19 20:54:36 +08:00
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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2016-04-24 19:34:41 +08:00
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* Change Logs:
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* Date Author Notes
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* 2010-05-17 swkyer first version
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2019-07-19 20:54:36 +08:00
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* 2010-09-04 bernard porting to JZ47xx
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* 2019-07-19 Zhou Yanjie clean up code
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2016-04-24 19:34:41 +08:00
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*/
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2019-07-19 20:46:06 +08:00
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include "../common/mips_def.h"
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2016-04-24 19:34:41 +08:00
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#include "../common/stackframe.h"
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#include "stack.h"
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.section ".start", "ax"
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.set noreorder
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/* the program entry */
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.globl _start
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_start:
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.set noreorder
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la ra, _start
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li t1, 0x00800000
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mtc0 t1, CP0_CAUSE
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/* init cp0 registers. */
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li t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
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mtc0 t0, CP0_STATUS
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/* setup stack pointer */
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li sp, SYSTEM_STACK
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la gp, _gp
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/* init caches, assumes a 4way * 128set * 32byte I/D cache */
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mtc0 zero, CP0_TAGLO /* TAGLO reg */
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mtc0 zero, CP0_TAGHI /* TAGHI reg */
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li t0, 3 /* enable cache for kseg0 accesses */
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mtc0 t0, CP0_CONFIG /* CONFIG reg */
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la t0, 0x80000000 /* an idx op should use an unmappable address */
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ori t1, t0, 0x4000 /* 16kB cache */
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_cache_loop:
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cache 0x8, 0(t0) /* index store icache tag */
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cache 0x9, 0(t0) /* index store dcache tag */
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bne t0, t1, _cache_loop
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addiu t0, t0, 0x20 /* 32 bytes per cache line */
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nop
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/* invalidate BTB */
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mfc0 t0, CP0_CONFIG
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nop
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ori t0, 2
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mtc0 t0, CP0_CONFIG
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nop
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/* copy IRAM section */
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la t0, _iramcopy
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la t1, _iramstart
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la t2, _iramend
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_iram_loop:
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lw t3, 0(t0)
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sw t3, 0(t1)
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addiu t1, 4
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bne t1, t2, _iram_loop
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addiu t0, 4
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/* clear bss */
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la t0, __bss_start
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la t1, __bss_end
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_clr_bss_loop:
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sw zero, 0(t0)
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bne t0, t1, _clr_bss_loop
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addiu t0, t0, 4
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/* jump to RT-Thread RTOS */
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jal rtthread_startup
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nop
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/* restart, never die */
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j _start
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nop
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.set reorder
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.globl cp0_get_cause
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cp0_get_cause:
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mfc0 v0, CP0_CAUSE
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jr ra
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nop
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.globl cp0_get_status
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cp0_get_status:
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mfc0 v0, CP0_STATUS
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jr ra
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nop
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.globl cp0_get_hi
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cp0_get_hi:
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mfhi v0
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jr ra
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nop
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.globl cp0_get_lo
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cp0_get_lo:
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mflo v0
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jr ra
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nop
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.extern tlb_refill_handler
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.extern cache_error_handler
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/* Exception Handler */
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/* 0x0 - TLB refill handler */
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.section .vectors.1, "ax", %progbits
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j tlb_refill_handler
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nop
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/* 0x100 - Cache error handler */
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.section .vectors.2, "ax", %progbits
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j cache_error_handler
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nop
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/* 0x180 - Exception/Interrupt handler */
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.section .vectors.3, "ax", %progbits
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j _general_exception_handler
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nop
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/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
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.section .vectors.4, "ax", %progbits
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j _irq_handler
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nop
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.section .vectors, "ax", %progbits
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.extern mips_irq_handle
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/* general exception handler */
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_general_exception_handler:
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.set noreorder
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mfc0 k1, CP0_CAUSE
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andi k1, k1, 0x7c
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srl k1, k1, 2
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lw k0, sys_exception_handlers(k1)
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jr k0
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nop
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.set reorder
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/* interrupt handler */
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_irq_handler:
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.set noreorder
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la k0, mips_irq_handle
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jr k0
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nop
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.set reorder
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