323 lines
8.4 KiB
C
323 lines
8.4 KiB
C
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/*
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* Copyright 2019-2020 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_XECC_H_
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#define _FSL_XECC_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup xecc
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* @{
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*/
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/******************************************************************************
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* Definitions.
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*****************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief Driver version 2.0.0. */
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#define FSL_XECC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
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/*@}*/
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/*!
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* @brief XECC interrupt configuration structure, , xecc_interrupt_enable_t.
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*
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* This structure contains the settings for all of the XECC interrupt configurations.
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*/
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enum
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{
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kXECC_SingleErrorInterruptEnable = XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK, /*!< Single bit error interrupt enable*/
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kXECC_MultiErrorInterruptEnable = XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK, /*!< Multiple bit error interrupt enable*/
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kXECC_AllInterruptsEnable =
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XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK | XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK, /*!< all interrupts enable */
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};
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/*!
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* @brief XECC interrupt status configuration structure, xecc_interrupt_status_enable_t.
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*
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* This structure contains the settings for all of the XECC interrupt status configurations.
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*/
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enum
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{
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kXECC_SingleErrorInterruptStatusEnable =
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XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK, /*!< Single bit error interrupt status enable*/
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kXECC_MultiErrorInterruptStatusEnable =
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XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK, /*!< Multiple bits error interrupt status enable*/
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kXECC_AllInterruptsStatusEnable = XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK |
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XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK, /*!< all interrupts enable */
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};
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/*!
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* @brief XECC status flags, xecc_interrupt_status_t.
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*
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* This provides constants for the XECC status flags for use in the XECC functions.
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*/
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enum
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{
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kXECC_SingleErrorInterruptFlag =
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XECC_ERR_STATUS_SINGLE_ERR_MASK, /*!< Single bit error interrupt happens on read data*/
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kXECC_MultiErrorInterruptFlag =
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XECC_ERR_STATUS_MULTI_ERR_MASK, /*!< Multiple bits error interrupt happens on read data*/
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kXECC_AllInterruptsFlag =
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XECC_ERR_STATUS_SINGLE_ERR_MASK | XECC_ERR_STATUS_MULTI_ERR_MASK, /*!< all interrupts happens on read data*/
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};
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/*! @brief XECC user configuration.*/
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typedef struct _xecc_config
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{
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bool enableXECC; /*!< Enable the XECC function. */
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bool enableWriteECC; /*!< Enable write ECC function. */
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bool enableReadECC; /*!< Enable read ECC function. */
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bool enableSwap; /*!< Enable swap function. */
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/*!< The minimum ECC region range is 4k, so the lower 12 bits of this register must be 0.*/
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uint32_t Region0BaseAddress; /*!< ECC region 0 base address. */
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uint32_t Region0EndAddress; /*!< ECC region 0 end address. */
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uint32_t Region1BaseAddress; /*!< ECC region 1 base address. */
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uint32_t Region1EndAddress; /*!< ECC region 1 end address. */
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uint32_t Region2BaseAddress; /*!< ECC region 2 base address. */
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uint32_t Region2EndAddress; /*!< ECC region 2 end address. */
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uint32_t Region3BaseAddress; /*!< ECC region 3 base address. */
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uint32_t Region3EndAddress; /*!< ECC region 3 end address. */
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} xecc_config_t;
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/*! @brief XECC single error information, including single error address, ECC code, error data, error bit
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* position and error bit field */
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typedef struct _xecc_single_error_info
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{
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uint32_t singleErrorAddress; /*!< Single error address */
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uint32_t singleErrorData; /*!< Single error read data */
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uint32_t singleErrorEccCode; /*!< Single error ECC code */
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uint32_t singleErrorBitPos; /*!< Single error bit postion */
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uint32_t singleErrorBitField; /*!< Single error bit field */
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} xecc_single_error_info_t;
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/*! @brief XECC multiple error information, including multiple error address, ECC code, error data and error bit field
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*/
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typedef struct _xecc_multi_error_info
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{
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uint32_t multiErrorAddress; /*!< Multiple error address */
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uint32_t multiErrorData; /*!< Multiple error read data */
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uint32_t multiErrorEccCode; /*!< Multiple error ECC code */
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uint32_t multiErrorBitField; /*!< Single error bit field */
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} xecc_multi_error_info_t;
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/*******************************************************************************
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* APIs
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief XECC module initialization function.
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*
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* @param base XECC base address.
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* @param config pointer to the XECC configuration structure.
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*/
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void XECC_Init(XECC_Type *base, const xecc_config_t *config);
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/*!
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* @brief Deinitializes the XECC.
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*
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* @param base XECC base address.
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*/
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void XECC_Deinit(XECC_Type *base);
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/*!
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* @brief Sets the XECC configuration structure to default values.
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*
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* @param config pointer to the XECC configuration structure.
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*/
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void XECC_GetDefaultConfig(xecc_config_t *config);
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/* @} */
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/*!
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* @name Status
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* @{
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*/
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/*!
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* @brief Gets XECC status flags.
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*
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* @param base XECC peripheral base address.
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* @return XECC status flags.
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*/
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static inline uint32_t XECC_GetStatusFlags(XECC_Type *base)
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{
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return base->ERR_STATUS & (uint32_t)kXECC_AllInterruptsFlag;
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}
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/*!
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* @brief XECC module clear interrupt status.
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*
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* @param base XECC base address.
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* @param mask status to clear from xecc_interrupt_status_t.
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*/
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static inline void XECC_ClearStatusFlags(XECC_Type *base, uint32_t mask)
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{
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base->ERR_STATUS = mask;
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}
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/*!
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* @brief XECC module enable interrupt status.
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*
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* @param base XECC base address.
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* @param mask status to enable from xecc_interrupt_status_enable_t.
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*/
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static inline void XECC_EnableInterruptStatus(XECC_Type *base, uint32_t mask)
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{
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base->ERR_STAT_EN |= mask;
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}
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/*!
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* @brief XECC module disable interrupt status.
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*
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* @param base XECC base address.
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* @param mask status to disable from xecc_interrupt_status_enable_t.
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*/
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static inline void XECC_DisableInterruptStatus(XECC_Type *base, uint32_t mask)
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{
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base->ERR_STAT_EN &= ~mask;
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}
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/* @} */
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/*!
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* @name Interrupts
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* @{
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*/
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/*!
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* @brief XECC module enable interrupt.
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*
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* @param base XECC base address.
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* @param mask The interrupts to enable from xecc_interrupt_enable_t.
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*/
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static inline void XECC_EnableInterrupts(XECC_Type *base, uint32_t mask)
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{
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base->ERR_SIG_EN |= mask;
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}
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/*!
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* @brief XECC module disable interrupt.
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*
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* @param base XECC base address.
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* @param mask The interrupts to disable from xecc_interrupt_enable_t.
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*/
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static inline void XECC_DisableInterrupts(XECC_Type *base, uint32_t mask)
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{
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base->ERR_SIG_EN &= ~mask;
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}
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/* @} */
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/*!
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* @name functional
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* @{
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*/
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/*!
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* @brief XECC module write ECC function enable.
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*
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* @param base XECC base address.
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* @param enable enable or disable.
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*/
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static inline void XECC_WriteECCEnable(XECC_Type *base, bool enable)
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{
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if (enable)
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{
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base->ECC_CTRL |= XECC_ECC_CTRL_WECC_EN(1);
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}
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else
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{
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base->ECC_CTRL |= XECC_ECC_CTRL_WECC_EN(0);
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}
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}
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/*!
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* @brief XECC module read ECC function enable.
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*
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* @param base XECC base address.
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* @param enable enable or disable.
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*/
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static inline void XECC_ReadECCEnable(XECC_Type *base, bool enable)
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{
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if (enable)
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{
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base->ECC_CTRL |= XECC_ECC_CTRL_RECC_EN(1);
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}
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else
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{
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base->ECC_CTRL |= XECC_ECC_CTRL_RECC_EN(0);
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}
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}
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/*!
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* @brief XECC module swap data enable.
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*
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* @param base XECC base address.
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* @param enable enable or disable.
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*/
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static inline void XECC_SwapECCEnable(XECC_Type *base, bool enable)
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{
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if (enable)
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{
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base->ECC_CTRL |= XECC_ECC_CTRL_SWAP_EN(1);
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}
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else
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{
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base->ECC_CTRL |= XECC_ECC_CTRL_SWAP_EN(0);
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}
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}
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/*!
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* @brief XECC module error injection.
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*
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* @param base XECC base address.
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* @param errordata error data.
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* @param erroreccdata ecc code.
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* @retval kStatus_Success.
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*/
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status_t XECC_ErrorInjection(XECC_Type *base, uint32_t errordata, uint8_t erroreccdata);
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/*!
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* @brief XECC module get single error information.
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*
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* @param base XECC base address.
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* @param info single error information.
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*/
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void XECC_GetSingleErrorInfo(XECC_Type *base, xecc_single_error_info_t *info);
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/*!
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* @brief XECC module get multiple error information.
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*
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* @param base XECC base address.
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* @param info multiple error information.
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*/
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void XECC_GetMultiErrorInfo(XECC_Type *base, xecc_multi_error_info_t *info);
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/*! @}*/
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif
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