407 lines
12 KiB
C
407 lines
12 KiB
C
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/*
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* Copyright 2019-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_ocotp.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.ocotp"
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#endif
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#if defined(FSL_FEATURE_OCOTP_HAS_STATUS) && FSL_FEATURE_OCOTP_HAS_STATUS
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#define OCOTP_STATUS_READ_DED_MASK \
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(OCOTP_OUT_STATUS0_DED0_MASK | OCOTP_OUT_STATUS0_DED1_MASK | OCOTP_OUT_STATUS0_DED2_MASK | \
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OCOTP_OUT_STATUS0_DED3_MASK)
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#endif
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/* Wait time should be not less than 150ns . */
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#define OCOTP_TIMING_WAIT_NS (uint64_t)150
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/* Relex time should be not less than 100ns . */
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#define OCOTP_TIMING_RELEX_NS (uint64_t)100
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/* Program time should be rang from 9000ns~11000ns. */
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#define OCOTP_TIMING_PROGRAM_NS (uint64_t)10000
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/* Read time should be less than 40ns. */
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#define OCOTP_TIMING_READ_NS (uint64_t)40
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/* Unlock key is 0x3E77. */
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#define OCOTP_WRITE_UNLOCK_KEY (0x3E77)
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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/*!
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* @brief Set read timing configuration.
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*
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* @param base OCOTP peripheral base addess.
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* @param timingConfig configuration of timing.
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*/
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static void OCOTP_SetReadTiming(OCOTP_Type *base, ocotp_timing_t timingConfig);
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/*!
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* @brief Set write timing configuration.
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*
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* @param base OCOTP peripheral base addess.
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* @param timingConfig configuration of timing.
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*/
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static void OCOTP_SetWriteTiming(OCOTP_Type *base, ocotp_timing_t timingConfig);
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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/* Timing configuration for OCOTP controller. */
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static ocotp_timing_t s_timingConfig;
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#endif
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/*******************************************************************************
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* Code
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*******************************************************************************/
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/* Reload the shadow register. */
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status_t OCOTP_ReloadShadowRegister(OCOTP_Type *base)
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{
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assert(NULL != base);
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status_t status = kStatus_Success;
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/* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */
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while (OCOTP_CheckBusyStatus(base))
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{
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}
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/* Clear access error status bit. */
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OCOTP_ClearErrorStatus(base);
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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/* Set the read timing. */
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OCOTP_SetReadTiming(base, s_timingConfig);
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/* Wait for the OCOTP controller not busy. */
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while (OCOTP_CheckBusyStatus(base))
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{
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}
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#endif
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#if defined(OCOTP_OUT_STATUS0_DED_RELOAD_MASK)
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/* Clear reload error status. */
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base->OUT_STATUS0_CLR = OCOTP_OUT_STATUS0_DED_RELOAD_MASK;
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#endif
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/* Set reload bit. */
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base->CTRL_SET = OCOTP_CTRL_RELOAD_SHADOWS(1);
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/* Wait for the OCOTP controller not busy. */
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while (OCOTP_CheckBusyStatus(base))
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{
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}
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/* Wait for shadow register reload complete. this bit will be auto clear by OCOTP once operation is complete. */
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while (OCOTP_CTRL_RELOAD_SHADOWS_MASK == (base->CTRL & OCOTP_CTRL_RELOAD_SHADOWS_MASK))
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{
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}
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#if defined(OCOTP_OUT_STATUS0_DED_RELOAD_MASK)
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if ((base->OUT_STATUS0 & OCOTP_OUT_STATUS0_DED_RELOAD_MASK) != 0U)
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{
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status = kStatus_OCOTP_ReloadError;
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}
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#endif
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return status;
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}
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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static void OCOTP_SetReadTiming(OCOTP_Type *base, ocotp_timing_t timingConfig)
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{
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uint32_t timingValue = base->TIMING;
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timingValue &= ~(OCOTP_TIMING_RELAX_MASK | OCOTP_TIMING_STROBE_READ_MASK | OCOTP_TIMING_WAIT_MASK);
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timingValue |= OCOTP_TIMING_RELAX(timingConfig.relax) | OCOTP_TIMING_STROBE_READ(timingConfig.strobe_read) |
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OCOTP_TIMING_WAIT(timingConfig.wait);
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base->TIMING = timingValue;
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}
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static void OCOTP_SetWriteTiming(OCOTP_Type *base, ocotp_timing_t timingConfig)
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{
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uint32_t timingValue = base->TIMING;
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timingValue &= ~(OCOTP_TIMING_RELAX_MASK | OCOTP_TIMING_STROBE_PROG_MASK | OCOTP_TIMING_WAIT_MASK);
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timingValue |= OCOTP_TIMING_RELAX(timingConfig.relax) | OCOTP_TIMING_STROBE_PROG(timingConfig.strobe_prog) |
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OCOTP_TIMING_WAIT(timingConfig.wait);
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base->TIMING = timingValue;
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}
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#endif
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/* Initializes OCOTP controller. */
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void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz)
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{
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assert(NULL != base);
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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assert(0UL != srcClock_Hz);
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#endif
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable OCOTP clock */
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CLOCK_EnableClock(kCLOCK_Ocotp);
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#endif
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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/* tWait time shoule be higher than OCOTP_TIMING_WAIT_NS. */
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s_timingConfig.wait = (uint32_t)((OCOTP_TIMING_WAIT_NS * srcClock_Hz + 1000000000U) / 1000000000U - 1U);
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/* tRelax time shoule be higher than OCOTP_TIMING_RELEX_NS. */
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s_timingConfig.relax = (uint32_t)((OCOTP_TIMING_RELEX_NS * srcClock_Hz + 1000000000U) / 1000000000U - 1U);
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/* tStrobe_prog time should be close to OCOTP_TIMING_PROGRAM_NS, only add half of 1000000000. */
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s_timingConfig.strobe_prog = (uint32_t)((OCOTP_TIMING_PROGRAM_NS * srcClock_Hz + 500000000U) / 1000000000U) +
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2U * (s_timingConfig.relax + 1U) - 1U;
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/* tStrobe_read time should be higher than OCOTP_TIMING_READ_NS. */
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s_timingConfig.strobe_read = (uint32_t)((OCOTP_TIMING_READ_NS * srcClock_Hz + 1000000000U) / 1000000000U) +
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2U * (s_timingConfig.relax + 1U) - 1U;
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#endif
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}
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/* De-init OCOTP controller. */
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void OCOTP_Deinit(OCOTP_Type *base)
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{
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assert(NULL != base);
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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s_timingConfig.wait = 0UL;
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s_timingConfig.relax = 0UL;
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s_timingConfig.strobe_prog = 0UL;
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s_timingConfig.strobe_read = 0UL;
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#endif
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable OCOTP clock */
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CLOCK_DisableClock(kCLOCK_Ocotp);
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#endif
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}
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/* Read the fuse shadow register. */
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uint32_t OCOTP_ReadFuseShadowRegister(OCOTP_Type *base, uint32_t address)
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{
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assert(NULL != base);
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uint32_t data = 0U;
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(void)OCOTP_ReadFuseShadowRegisterExt(base, address, &data, 1);
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return data;
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}
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status_t OCOTP_ReadFuseShadowRegisterExt(OCOTP_Type *base, uint32_t address, uint32_t *data, uint8_t fuseWords)
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{
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assert((fuseWords > 0U) && (fuseWords <= OCOTP_READ_FUSE_DATA_COUNT));
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assert(NULL != data);
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status_t status = kStatus_Success;
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#if (OCOTP_READ_FUSE_DATA_COUNT > 1U)
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uint32_t i;
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#endif
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/* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */
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while (OCOTP_CheckBusyStatus(base))
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{
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}
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/* If ERROR bit was set, clear access error status bit. */
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if (OCOTP_CheckErrorStatus(base))
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{
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OCOTP_ClearErrorStatus(base);
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}
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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/* Set the read timing. */
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OCOTP_SetReadTiming(base, s_timingConfig);
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/* Wait for busy bit is cleared. */
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while (OCOTP_CheckBusyStatus(base))
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{
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}
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/* Clear access error status bit. */
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if (OCOTP_CheckErrorStatus(base))
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{
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OCOTP_ClearErrorStatus(base);
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}
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#endif
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#if defined(OCOTP_STATUS_READ_DED_MASK)
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/* Clear error flags. */
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base->OUT_STATUS0_CLR = OCOTP_STATUS_READ_DED_MASK;
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#endif
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/* Write requested address to register. */
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base->CTRL_CLR = OCOTP_CTRL_CLR_ADDR_MASK;
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base->CTRL_SET = OCOTP_CTRL_SET_ADDR(address);
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/* Set OCOTP auto read enable. */
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#if defined(OCOTP_READ_CTRL_READ_NUM_MASK)
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base->READ_CTRL = (base->READ_CTRL & ~(OCOTP_READ_CTRL_READ_NUM_MASK)) |
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OCOTP_READ_CTRL_READ_NUM((uint32_t)fuseWords - 1U) | OCOTP_READ_CTRL_READ_FUSE_MASK;
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#else
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base->READ_CTRL |= OCOTP_READ_CTRL_READ_FUSE_MASK;
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#endif
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/* Wait for busy bit is cleared, and no error occurred on controller. */
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while (OCOTP_CheckBusyStatus(base))
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{
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}
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/* If ERROR bit was set, this may be mean that the accsee to the register was wrong. */
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if (OCOTP_CheckErrorStatus(base))
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{
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/* Clear access error status bit. */
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OCOTP_ClearErrorStatus(base);
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status = kStatus_OCOTP_AccessError;
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}
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#if defined(OCOTP_STATUS_READ_DED_MASK)
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if ((base->OUT_STATUS0 & OCOTP_STATUS_READ_DED_MASK) != 0U)
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{
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status = kStatus_Fail;
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}
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#endif
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#if (OCOTP_READ_FUSE_DATA_COUNT == 1U)
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*data = base->READ_FUSE_DATA;
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#else
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for (i = 0; i < fuseWords; i++)
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{
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data[i] = base->READ_FUSE_DATAS[i].READ_FUSE_DATA;
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}
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#endif
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return status;
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}
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/* Write the fuse shadow register. */
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status_t OCOTP_WriteFuseShadowRegister(OCOTP_Type *base, uint32_t address, uint32_t data)
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{
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return OCOTP_WriteFuseShadowRegisterWithLock(base, address, data, false);
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}
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status_t OCOTP_WriteFuseShadowRegisterWithLock(OCOTP_Type *base, uint32_t address, uint32_t data, bool lock)
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{
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assert(NULL != base);
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status_t status = kStatus_Success;
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#if defined(FSL_FEATURE_OCOTP_HAS_STATUS) && FSL_FEATURE_OCOTP_HAS_STATUS
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uint32_t regStatus;
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#endif
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#if !(defined(FSL_FEATURE_OCOTP_HAS_WORDLOCK) && FSL_FEATURE_OCOTP_HAS_WORDLOCK)
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if (lock)
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{
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return kStatus_InvalidArgument;
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}
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#endif
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/* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */
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while (OCOTP_CheckBusyStatus(base))
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{
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}
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/* Clear access error status bit. */
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if (OCOTP_CheckErrorStatus(base))
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{
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OCOTP_ClearErrorStatus(base);
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}
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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/* Set write timing for OCOTP controller. */
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OCOTP_SetWriteTiming(base, s_timingConfig);
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/* Wait for busy bit is cleared. */
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while (OCOTP_CheckBusyStatus(base))
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{
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}
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/* Clear access error status bit. */
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if (OCOTP_CheckErrorStatus(base))
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{
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OCOTP_ClearErrorStatus(base);
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}
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#endif
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#if defined(FSL_FEATURE_OCOTP_HAS_STATUS) && FSL_FEATURE_OCOTP_HAS_STATUS
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/* Clear errors. */
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base->OUT_STATUS0_CLR = (OCOTP_OUT_STATUS0_PROGFAIL_MASK | OCOTP_OUT_STATUS0_LOCKED_MASK);
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#endif
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/* Write requested address and unlock key to register. */
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#if (defined(FSL_FEATURE_OCOTP_HAS_WORDLOCK) && FSL_FEATURE_OCOTP_HAS_WORDLOCK)
|
||
|
|
base->CTRL_CLR = OCOTP_CTRL_CLR_ADDR_MASK | OCOTP_CTRL_WR_UNLOCK_MASK | OCOTP_CTRL_WORDLOCK_MASK;
|
||
|
|
#else
|
||
|
|
base->CTRL_CLR = OCOTP_CTRL_CLR_ADDR_MASK | OCOTP_CTRL_WR_UNLOCK_MASK;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if (defined(FSL_FEATURE_OCOTP_HAS_WORDLOCK) && FSL_FEATURE_OCOTP_HAS_WORDLOCK)
|
||
|
|
if (lock)
|
||
|
|
{
|
||
|
|
base->CTRL_SET =
|
||
|
|
OCOTP_CTRL_SET_ADDR(address) | OCOTP_CTRL_WR_UNLOCK(OCOTP_WRITE_UNLOCK_KEY) | OCOTP_CTRL_WORDLOCK_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
base->CTRL_SET = OCOTP_CTRL_SET_ADDR(address) | OCOTP_CTRL_WR_UNLOCK(OCOTP_WRITE_UNLOCK_KEY);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Write data to register. */
|
||
|
|
base->DATA = data;
|
||
|
|
|
||
|
|
/* Wait for busy bit is cleared, and no error occurred on controller. */
|
||
|
|
while (OCOTP_CheckBusyStatus(base))
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If ERROR bit was set, this may be mean that the accsee to the register was wrong. */
|
||
|
|
if (OCOTP_CheckErrorStatus(base))
|
||
|
|
{
|
||
|
|
/* Clear access error status bit. */
|
||
|
|
OCOTP_ClearErrorStatus(base);
|
||
|
|
|
||
|
|
status = kStatus_OCOTP_AccessError;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(FSL_FEATURE_OCOTP_HAS_STATUS) && FSL_FEATURE_OCOTP_HAS_STATUS
|
||
|
|
regStatus = base->OUT_STATUS0;
|
||
|
|
|
||
|
|
if ((regStatus & OCOTP_OUT_STATUS0_PROGFAIL_MASK) != 0U)
|
||
|
|
{
|
||
|
|
status = kStatus_OCOTP_ProgramFail;
|
||
|
|
}
|
||
|
|
else if ((regStatus & OCOTP_OUT_STATUS0_LOCKED_MASK) != 0U)
|
||
|
|
{
|
||
|
|
status = kStatus_OCOTP_Locked;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* For MISRA rules. */
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
if (kStatus_Success == status)
|
||
|
|
{
|
||
|
|
/* Reload the fuse register. */
|
||
|
|
status = OCOTP_ReloadShadowRegister(base);
|
||
|
|
}
|
||
|
|
|
||
|
|
return status;
|
||
|
|
}
|