245 lines
12 KiB
C
245 lines
12 KiB
C
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//###########################################################################
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//
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// FILE: hw_i2c.h
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//
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// TITLE: Definitions for the C28x I2C registers.
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef __HW_I2C_H__
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#define __HW_I2C_H__
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//*****************************************************************************
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//
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// The following are defines for the I2C register offsets
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//
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//*****************************************************************************
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#define I2C_O_OAR 0x0 // I2C Own address
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#define I2C_O_IER 0x1 // I2C Interrupt Enable
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#define I2C_O_STR 0x2 // I2C Status
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#define I2C_O_CLKL 0x3 // I2C Clock low-time divider
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#define I2C_O_CLKH 0x4 // I2C Clock high-time divider
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#define I2C_O_CNT 0x5 // I2C Data count
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#define I2C_O_DRR 0x6 // I2C Data receive
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#define I2C_O_SAR 0x7 // I2C Slave address
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#define I2C_O_DXR 0x8 // I2C Data Transmit
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#define I2C_O_MDR 0x9 // I2C Mode
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#define I2C_O_ISRC 0xA // I2C Interrupt Source
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#define I2C_O_EMDR 0xB // I2C Extended Mode
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#define I2C_O_PSC 0xC // I2C Prescaler
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#define I2C_O_FFTX 0x20 // I2C FIFO Transmit
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#define I2C_O_FFRX 0x21 // I2C FIFO Receive
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2COAR register
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//
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//*****************************************************************************
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#define I2C_OAR_OAR_S 0
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#define I2C_OAR_OAR_M 0x3FF // I2C Own address
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CIER register
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//
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//*****************************************************************************
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#define I2C_IER_ARBL 0x1 // Arbitration-lost interrupt
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// enable
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#define I2C_IER_NACK 0x2 // No-acknowledgment interrupt
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// enable
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#define I2C_IER_ARDY 0x4 // Register-access-ready interrupt
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// enable
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#define I2C_IER_RRDY 0x8 // Receive-data-ready interrupt
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// enable
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#define I2C_IER_XRDY 0x10 // Transmit-data-ready interrupt
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// enable
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#define I2C_IER_SCD 0x20 // Stop condition detected
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// interrupt enable
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#define I2C_IER_AAS 0x40 // Addressed as slave interrupt
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// enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CSTR register
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//
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//*****************************************************************************
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#define I2C_STR_ARBL 0x1 // Arbitration-lost interrupt flag
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// bit
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#define I2C_STR_NACK 0x2 // No-acknowledgment interrupt
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// flag bit.
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#define I2C_STR_ARDY 0x4 // Register-access-ready interrupt
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// flag bit
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#define I2C_STR_RRDY 0x8 // Receive-data-ready interrupt
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// flag bit.
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#define I2C_STR_XRDY 0x10 // Transmit-data-ready interrupt
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// flag bit.
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#define I2C_STR_SCD 0x20 // Stop condition detected bit.
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#define I2C_STR_AD0 0x100 // Address 0 bits
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#define I2C_STR_AAS 0x200 // Addressed-as-slave bit
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#define I2C_STR_XSMT 0x400 // Transmit shift register empty
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// bit.
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#define I2C_STR_RSFULL 0x800 // Receive shift register full
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// bit.
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#define I2C_STR_BB 0x1000 // Bus busy bit.
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#define I2C_STR_NACKSNT 0x2000 // NACK sent bit.
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#define I2C_STR_SDIR 0x4000 // Slave direction bit
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CCLKL register
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//
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//*****************************************************************************
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#define I2C_CLKL_I2CCLKL_S 0
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#define I2C_CLKL_I2CCLKL_M 0xFFFF // Clock low-time divide-down
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// value.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CCLKH register
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//
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//*****************************************************************************
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#define I2C_CLKH_I2CCLKH_S 0
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#define I2C_CLKH_I2CCLKH_M 0xFFFF // Clock high-time divide-down
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// value.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CCNT register
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//
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//*****************************************************************************
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#define I2C_CNT_I2CCNT_S 0
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#define I2C_CNT_I2CCNT_M 0xFFFF // Data count value.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CDRR register
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//
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//*****************************************************************************
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#define I2C_DRR_DATA_S 0
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#define I2C_DRR_DATA_M 0xFF // Receive data
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CSAR register
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//
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//*****************************************************************************
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#define I2C_SAR_SAR_S 0
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#define I2C_SAR_SAR_M 0x3FF // Slave Address
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CDXR register
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//
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//*****************************************************************************
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#define I2C_DXR_DATA_S 0
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#define I2C_DXR_DATA_M 0xFF // Transmit data
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CMDR register
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//
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//*****************************************************************************
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#define I2C_MDR_BC_S 0
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#define I2C_MDR_BC_M 0x7 // Bit count bits.
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#define I2C_MDR_FDF 0x8 // Free Data Format
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#define I2C_MDR_STB 0x10 // START Byte Mode
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#define I2C_MDR_IRS 0x20 // I2C Module Reset
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#define I2C_MDR_DLB 0x40 // Digital Loopback Mode
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#define I2C_MDR_RM 0x80 // Repeat Mode
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#define I2C_MDR_XA 0x100 // Expanded Address Mode
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#define I2C_MDR_TRX 0x200 // Transmitter Mode
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#define I2C_MDR_MST 0x400 // Master Mode
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#define I2C_MDR_STP 0x800 // STOP Condition
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#define I2C_MDR_STT 0x2000 // START condition bit
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#define I2C_MDR_FREE 0x4000 // Debug Action
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#define I2C_MDR_NACKMOD 0x8000 // NACK mode bit
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CISRC register
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//
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//*****************************************************************************
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#define I2C_ISRC_INTCODE_S 0
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#define I2C_ISRC_INTCODE_M 0x7 // Interrupt code bits.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CEMDR register
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//
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//*****************************************************************************
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#define I2C_EMDR_BC 0x1 // Backwards compatibility mode
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CPSC register
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//
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//*****************************************************************************
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#define I2C_PSC_IPSC_S 0
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#define I2C_PSC_IPSC_M 0xFF // I2C Prescaler Divide Down
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CFFTX register
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//
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//*****************************************************************************
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#define I2C_FFTX_TXFFIL_S 0
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#define I2C_FFTX_TXFFIL_M 0x1F // Transmit FIFO Interrupt Level
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#define I2C_FFTX_TXFFIENA 0x20 // Transmit FIFO Interrupt Enable
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#define I2C_FFTX_TXFFINTCLR 0x40 // Transmit FIFO Interrupt Flag
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// Clear
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#define I2C_FFTX_TXFFINT 0x80 // Transmit FIFO Interrupt Flag
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#define I2C_FFTX_TXFFST_S 8
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#define I2C_FFTX_TXFFST_M 0x1F00 // Transmit FIFO Status
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#define I2C_FFTX_TXFFRST 0x2000 // Transmit FIFO Reset
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#define I2C_FFTX_I2CFFEN 0x4000 // Transmit FIFO Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CFFRX register
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//
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//*****************************************************************************
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#define I2C_FFRX_RXFFIL_S 0
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#define I2C_FFRX_RXFFIL_M 0x1F // Receive FIFO Interrupt Level
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#define I2C_FFRX_RXFFIENA 0x20 // Receive FIFO Interrupt Enable
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#define I2C_FFRX_RXFFINTCLR 0x40 // Receive FIFO Interrupt Flag
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// Clear
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#define I2C_FFRX_RXFFINT 0x80 // Receive FIFO Interrupt Flag
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#define I2C_FFRX_RXFFST_S 8
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#define I2C_FFRX_RXFFST_M 0x1F00 // Receive FIFO Status
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#define I2C_FFRX_RXFFRST 0x2000 // Receive FIFO Reset
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#endif
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