482 lines
18 KiB
C
482 lines
18 KiB
C
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/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_dma.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.lpc_dma"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for DMA.
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*
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* @param base DMA peripheral base address.
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*/
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static uint32_t DMA_GetInstance(DMA_Type *base);
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/*!
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* @brief Get virtual channel number.
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*
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* @param base DMA peripheral base address.
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*/
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static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Array to map DMA instance number to base pointer. */
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static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Array to map DMA instance number to clock name. */
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static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*! @brief Array to map DMA instance number to IRQ number. */
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static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
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/*! @brief Pointers to transfer handle for each DMA channel. */
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static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS];
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/*! @brief Static table of descriptors */
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#if defined(__ICCARM__)
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#pragma data_alignment = FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE
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static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0};
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#elif defined(__CC_ARM)
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__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)))
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static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0};
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#elif defined(__GNUC__)
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__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE)))
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static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0};
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#endif
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t DMA_GetInstance(DMA_Type *base)
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{
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int32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
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{
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if (s_dmaBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_dmaBases));
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return instance;
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}
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static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base)
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{
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uint32_t startChannel = 0, instance = 0;
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uint32_t i = 0;
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instance = DMA_GetInstance(base);
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/* Compute start channel */
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for (i = 0; i < instance; i++)
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{
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startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]);
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}
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return startChannel;
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}
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void DMA_Init(DMA_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* enable dma clock gate */
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CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* set descriptor table */
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base->SRAMBASE = (uint32_t)s_dma_descriptor_table;
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/* enable dma peripheral */
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base->CTRL |= DMA_CTRL_ENABLE_MASK;
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}
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void DMA_Deinit(DMA_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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CLOCK_DisableClock(s_dmaClockName[DMA_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Disable DMA peripheral */
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base->CTRL &= ~(DMA_CTRL_ENABLE_MASK);
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}
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void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)
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{
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assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger));
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uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
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DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK |
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DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK);
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tmp = base->CHANNEL[channel].CFG & (~tmp);
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tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
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base->CHANNEL[channel].CFG = tmp;
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}
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/*!
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* @brief Gets the remaining bytes of the current DMA descriptor transfer.
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*
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* @param base DMA peripheral base address.
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* @param channel DMA channel number.
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* @return The number of bytes which have not been transferred yet.
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*/
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uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
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{
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assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base));
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/* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes
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* impossible to distinguish between:
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* - transfer finishes (represented by value '0x3FF')
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* - and remaining 1024 bytes to transfer (value 0x3FF)
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* for all descriptor in chain, except the last one.
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* If you decide to use this function, please use 1023 transfers as maximal value */
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/* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
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if ((!DMA_ChannelIsActive(base, channel)) &&
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(0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
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DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)))
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{
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return 0;
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}
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return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
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DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) +
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1;
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}
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static void DMA_SetupDescriptor(
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dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc)
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{
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desc->xfercfg = xfercfg;
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desc->srcEndAddr = srcEndAddr;
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desc->dstEndAddr = dstEndAddr;
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desc->linkToNextDesc = nextDesc;
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}
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/* Verify and convert dma_xfercfg_t to XFERCFG register */
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static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
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{
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assert(xfercfg != NULL);
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/* check source increment */
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assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4));
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/* check destination increment */
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assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4));
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/* check data width */
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assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4));
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/* check transfer count */
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assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
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uint32_t xfer = 0, tmp;
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/* set valid flag - descriptor is ready now */
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xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0);
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/* set reload - allow link to next descriptor */
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xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0);
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/* set swtrig flag - start transfer */
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xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0);
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/* set transfer count */
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xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0);
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/* set INTA */
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xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0);
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/* set INTB */
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xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0);
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/* set data width */
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tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1;
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xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp);
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/* set source increment value */
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tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc;
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xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp);
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/* set destination increment value */
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tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc;
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xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp);
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/* set transfer count */
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xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
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/* store xferCFG */
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*xfercfg_addr = xfer;
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}
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void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc)
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{
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uint32_t xfercfg_reg = 0;
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assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg));
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assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
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assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
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assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16));
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/* Setup channel configuration */
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DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
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/* Set descriptor structure */
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DMA_SetupDescriptor(
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desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
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(uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc);
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}
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void DMA_AbortTransfer(dma_handle_t *handle)
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{
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assert(NULL != handle);
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DMA_DisableChannel(handle->base, handle->channel);
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while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel)))
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{
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}
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DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel);
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DMA_EnableChannel(handle->base, handle->channel);
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}
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void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
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{
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assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)));
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int32_t dmaInstance;
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uint32_t startChannel = 0;
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/* base address is invalid DMA instance */
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dmaInstance = DMA_GetInstance(base);
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startChannel = DMA_GetVirtualStartChannel(base);
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memset(handle, 0, sizeof(*handle));
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handle->base = base;
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handle->channel = channel;
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s_DMAHandle[startChannel + channel] = handle;
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/* Enable NVIC interrupt */
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EnableIRQ(s_dmaIRQNumber[dmaInstance]);
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}
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void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)
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{
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assert(handle != NULL);
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handle->callback = callback;
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handle->userData = userData;
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}
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void DMA_PrepareTransfer(dma_transfer_config_t *config,
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void *srcAddr,
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void *dstAddr,
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uint32_t byteWidth,
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uint32_t transferBytes,
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dma_transfer_type_t type,
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void *nextDesc)
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{
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uint32_t xfer_count;
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assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
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assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
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/* check max */
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xfer_count = transferBytes / byteWidth;
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assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth));
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memset(config, 0, sizeof(*config));
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switch (type)
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{
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case kDMA_MemoryToMemory:
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config->xfercfg.srcInc = 1;
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config->xfercfg.dstInc = 1;
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config->isPeriph = false;
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break;
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case kDMA_PeripheralToMemory:
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/* Peripheral register - source doesn't increment */
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config->xfercfg.srcInc = 0;
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config->xfercfg.dstInc = 1;
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config->isPeriph = true;
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break;
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case kDMA_MemoryToPeripheral:
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/* Peripheral register - destination doesn't increment */
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config->xfercfg.srcInc = 1;
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config->xfercfg.dstInc = 0;
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config->isPeriph = true;
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break;
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case kDMA_StaticToStatic:
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config->xfercfg.srcInc = 0;
|
||
|
|
config->xfercfg.dstInc = 0;
|
||
|
|
config->isPeriph = true;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
config->dstAddr = (uint8_t *)dstAddr;
|
||
|
|
config->srcAddr = (uint8_t *)srcAddr;
|
||
|
|
config->nextDesc = (uint8_t *)nextDesc;
|
||
|
|
config->xfercfg.transferCount = xfer_count;
|
||
|
|
config->xfercfg.byteWidth = byteWidth;
|
||
|
|
config->xfercfg.intA = true;
|
||
|
|
config->xfercfg.reload = nextDesc != NULL;
|
||
|
|
config->xfercfg.valid = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
|
||
|
|
{
|
||
|
|
assert((NULL != handle) && (NULL != config));
|
||
|
|
uint32_t instance = DMA_GetInstance(handle->base);
|
||
|
|
|
||
|
|
/* Previous transfer has not finished */
|
||
|
|
if (DMA_ChannelIsActive(handle->base, handle->channel))
|
||
|
|
{
|
||
|
|
return kStatus_DMA_Busy;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* enable/disable peripheral request */
|
||
|
|
if (config->isPeriph)
|
||
|
|
{
|
||
|
|
DMA_EnableChannelPeriphRq(handle->base, handle->channel);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
DMA_DisableChannelPeriphRq(handle->base, handle->channel);
|
||
|
|
}
|
||
|
|
|
||
|
|
DMA_CreateDescriptor(&(s_dma_descriptor_table[instance][handle->channel]), &config->xfercfg, config->srcAddr,
|
||
|
|
config->dstAddr, config->nextDesc);
|
||
|
|
|
||
|
|
return kStatus_Success;
|
||
|
|
}
|
||
|
|
|
||
|
|
void DMA_StartTransfer(dma_handle_t *handle)
|
||
|
|
{
|
||
|
|
assert(NULL != handle);
|
||
|
|
|
||
|
|
uint32_t instance = DMA_GetInstance(handle->base);
|
||
|
|
|
||
|
|
/* Enable channel interrupt */
|
||
|
|
DMA_EnableChannelInterrupts(handle->base, handle->channel);
|
||
|
|
|
||
|
|
/* If HW trigger is enabled - disable SW trigger */
|
||
|
|
if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
|
||
|
|
{
|
||
|
|
s_dma_descriptor_table[instance][handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK);
|
||
|
|
}
|
||
|
|
/* Otherwise enable SW trigger */
|
||
|
|
else
|
||
|
|
{
|
||
|
|
s_dma_descriptor_table[instance][handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set channel XFERCFG register according first channel descriptor. */
|
||
|
|
handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[instance][handle->channel].xfercfg;
|
||
|
|
/* At this moment, the channel ACTIVE bit is set and application cannot modify
|
||
|
|
* or start another transfer using this channel. Channel ACTIVE bit is cleared by
|
||
|
|
* 'AbortTransfer' function or when the transfer finishes */
|
||
|
|
}
|
||
|
|
|
||
|
|
void DMA_IRQHandle(DMA_Type *base)
|
||
|
|
{
|
||
|
|
dma_handle_t *handle;
|
||
|
|
int32_t channel_index;
|
||
|
|
uint32_t startChannel = DMA_GetVirtualStartChannel(base);
|
||
|
|
uint32_t i = 0;
|
||
|
|
|
||
|
|
/* Find channels that have completed transfer */
|
||
|
|
for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++)
|
||
|
|
{
|
||
|
|
handle = s_DMAHandle[i + startChannel];
|
||
|
|
/* Handle is not present */
|
||
|
|
if (NULL == handle)
|
||
|
|
{
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
channel_index = DMA_CHANNEL_INDEX(handle->channel);
|
||
|
|
/* Channel uses INTA flag */
|
||
|
|
if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index))
|
||
|
|
{
|
||
|
|
/* Clear INTA flag */
|
||
|
|
DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index));
|
||
|
|
if (handle->callback)
|
||
|
|
{
|
||
|
|
(handle->callback)(handle, handle->userData, true, kDMA_IntA);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* Channel uses INTB flag */
|
||
|
|
if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index))
|
||
|
|
{
|
||
|
|
/* Clear INTB flag */
|
||
|
|
DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index));
|
||
|
|
if (handle->callback)
|
||
|
|
{
|
||
|
|
(handle->callback)(handle, handle->userData, true, kDMA_IntB);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* Error flag */
|
||
|
|
if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index))
|
||
|
|
{
|
||
|
|
/* Clear error flag */
|
||
|
|
DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index));
|
||
|
|
if (handle->callback)
|
||
|
|
{
|
||
|
|
(handle->callback)(handle, handle->userData, false, kDMA_IntError);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void DMA0_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
DMA_IRQHandle(DMA0);
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(DMA1)
|
||
|
|
void DMA1_DriverIRQHandler(void)
|
||
|
|
{
|
||
|
|
DMA_IRQHandle(DMA1);
|
||
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||
|
|
exception return operation might vector to incorrect interrupt */
|
||
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||
|
|
__DSB();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
#endif
|