60 lines
2.3 KiB
C
60 lines
2.3 KiB
C
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/*
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* This file is part of FH8620 BSP for RT-Thread distribution.
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*
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* Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd.
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* All rights reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Visit http://www.fullhan.com to get contact with Fullhan.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef FH_PMU_H_
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#define FH_PMU_H_
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#include <rtdef.h>
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#define REG_PMU_CHIP_ID (0x000)
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#define REG_PMU_IP_VER (0x004)
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#define REG_PMU_FW_VER (0x008)
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#define REG_PMU_SYS_CTRL (0x00c)
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#define REG_PMU_PLL0_CTRL (0x010)
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#define REG_PMU_PLL1_CTRL (0x014)
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#define REG_PMU_ARC_CLK_GATE (0x018)
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#define REG_PMU_CLK_GATE (0x01c)
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#define REG_PMU_CLK_SEL (0x020)
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#define REG_PMU_CLK_DIV0 (0x024)
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#define REG_PMU_CLK_DIV1 (0x028)
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#define REG_PMU_CLK_DIV2 (0x02c)
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#define REG_PMU_CLK_DIV3 (0x030)
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#define REG_PMU_CLK_DIV4 (0x034)
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#define REG_PMU_CLK_DIV5 (0x038)
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#define REG_PMU_CLK_DIV6 (0x03c)
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#define REG_PMU_SWRST_MAIN_CTRL (0x040)
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#define REG_PMU_SWRST_AXI_CTRL (0x044)
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#define REG_PMU_SWRST_AHB_CTRL (0x048)
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#define REG_PMU_SWRST_APB_CTRL (0x04c)
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#define REG_PMU_VDAC_CTRL (0x050)
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#define REG_PMU_MAC_REF_CLK_CFG (0x0a4)
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int fh_pmu_read(rt_uint32_t offset,rt_uint32_t *value);
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int fh_pmu_write(rt_uint32_t offset, const rt_uint32_t value);
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int fh_pmu_write_mask(rt_uint32_t offset,const rt_uint32_t value, const rt_uint32_t mask);
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#endif /* FH_PMU_H_ */
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