2018-05-11 20:34:54 +08:00
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/*
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2018-05-17 14:43:02 +08:00
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* File : fsl_phy_fire.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
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2018-05-11 20:34:54 +08:00
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*
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2018-05-17 14:43:02 +08:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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2018-05-11 20:34:54 +08:00
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*
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2018-05-17 14:43:02 +08:00
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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2018-05-11 20:34:54 +08:00
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*
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2018-05-17 14:43:02 +08:00
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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2018-05-11 20:34:54 +08:00
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*
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2018-05-17 14:43:02 +08:00
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* Change Logs:
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* Date Author Notes
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* 2018-05-21 zylx first version
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2018-05-11 20:34:54 +08:00
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*/
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#include "fsl_phy_fire.h"
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2018-05-17 14:43:02 +08:00
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#include <rtthread.h>
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2018-05-11 20:34:54 +08:00
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2018-05-17 14:43:02 +08:00
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#define DBG_ENABLE
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2018-07-11 10:23:19 +08:00
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#define DBG_SECTION_NAME "PHY"
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2018-05-17 14:43:02 +08:00
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#define DBG_COLOR
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#define DBG_LEVEL DBG_LOG
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#include <rtdbg.h>
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2018-05-11 20:34:54 +08:00
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#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
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extern uint32_t ENET_GetInstance(ENET_Type *base);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to enet clocks for each instance. */
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extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
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{
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uint32_t bssReg;
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2018-05-17 14:43:02 +08:00
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uint32_t i;
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2018-05-11 20:34:54 +08:00
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uint32_t counter = PHY_TIMEOUT_COUNT;
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uint32_t idReg = 0;
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status_t result = kStatus_Success;
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uint32_t instance = ENET_GetInstance(base);
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uint32_t timeDelay;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Set SMI first. */
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CLOCK_EnableClock(s_enetClock[instance]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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ENET_SetSMI(base, srcClock_Hz, false);
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/* Initialization after PHY stars to work. */
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while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
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{
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PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
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2018-05-17 14:43:02 +08:00
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counter --;
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2018-05-11 20:34:54 +08:00
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}
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if (!counter)
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{
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return kStatus_Fail;
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}
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/* Reset PHY. */
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counter = PHY_TIMEOUT_COUNT;
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result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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if (result == kStatus_Success)
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{
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2018-05-17 14:43:02 +08:00
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for (i = 0x10000; i > 0; i--)
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{
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result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &bssReg);
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if (!(bssReg & PHY_BCTL_POWER_DOWN_MASK))
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{
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break;
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}
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}
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2018-05-11 20:34:54 +08:00
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2018-05-17 14:43:02 +08:00
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if (i != 0)
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2018-05-11 20:34:54 +08:00
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{
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2018-05-17 14:43:02 +08:00
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/* Set the negotiation. */
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result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
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(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
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PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
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2018-05-11 20:34:54 +08:00
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if (result == kStatus_Success)
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{
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2018-05-17 14:43:02 +08:00
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result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
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(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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if (result == kStatus_Success)
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2018-05-11 20:34:54 +08:00
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{
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2018-05-17 14:43:02 +08:00
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/* Check auto negotiation complete. */
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while (counter --)
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2018-05-11 20:34:54 +08:00
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{
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2018-05-17 14:43:02 +08:00
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result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
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if (result == kStatus_Success)
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2018-05-11 20:34:54 +08:00
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{
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2018-05-17 14:43:02 +08:00
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if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0))
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2018-05-11 20:34:54 +08:00
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{
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2018-05-17 14:43:02 +08:00
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rt_thread_delay(1);
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}
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else
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{
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dbg_log(DBG_LOG, "auto negotiation complete success\n");
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break;
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2018-05-11 20:34:54 +08:00
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}
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}
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}
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if (!counter)
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{
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2018-05-17 14:43:02 +08:00
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dbg_log(DBG_LOG, "auto negotiation complete falied\n");
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2018-05-11 20:34:54 +08:00
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return kStatus_PHY_AutoNegotiateFail;
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}
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2018-05-17 14:43:02 +08:00
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2018-05-11 20:34:54 +08:00
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}
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}
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}
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}
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return result;
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}
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status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
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{
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uint32_t counter;
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/* Clear the SMI interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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/* Starts a SMI write command. */
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ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
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/* Wait for SMI complete. */
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for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
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{
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if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
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{
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break;
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}
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}
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/* Check for timeout. */
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if (!counter)
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{
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return kStatus_PHY_SMIVisitTimeout;
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}
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/* Clear MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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return kStatus_Success;
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}
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status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
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{
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assert(dataPtr);
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uint32_t counter;
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/* Clear the MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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/* Starts a SMI read command operation. */
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ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
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/* Wait for MII complete. */
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for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
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{
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if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
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{
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break;
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}
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}
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/* Check for timeout. */
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if (!counter)
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{
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return kStatus_PHY_SMIVisitTimeout;
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}
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/* Get data from MII register. */
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*dataPtr = ENET_ReadSMIData(base);
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/* Clear MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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return kStatus_Success;
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}
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status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable)
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{
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status_t result;
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uint32_t data = 0;
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/* Set the loop mode. */
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if (enable)
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{
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if (mode == kPHY_LocalLoop)
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{
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if (speed == kPHY_Speed100M)
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{
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data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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else
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{
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2018-05-17 14:43:02 +08:00
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data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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2018-05-11 20:34:54 +08:00
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}
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2018-05-17 14:43:02 +08:00
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return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
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2018-05-11 20:34:54 +08:00
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}
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else
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{
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/* First read the current status in control register. */
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result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
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if (result == kStatus_Success)
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{
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return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
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}
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}
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}
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else
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{
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/* Disable the loop mode. */
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if (mode == kPHY_LocalLoop)
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{
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/* First read the current status in control register. */
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result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
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if (result == kStatus_Success)
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{
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data &= ~PHY_BCTL_LOOP_MASK;
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return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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else
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{
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/* First read the current status in control one register. */
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result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
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if (result == kStatus_Success)
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{
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return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
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}
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}
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}
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return result;
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}
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status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
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{
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assert(status);
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status_t result = kStatus_Success;
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uint32_t data;
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/* Read the basic status register. */
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result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
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if (result == kStatus_Success)
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{
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if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
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{
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/* link down. */
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*status = false;
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}
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else
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{
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/* link up. */
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*status = true;
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}
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}
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return result;
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}
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status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
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{
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assert(duplex);
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status_t result = kStatus_Success;
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uint32_t data, ctlReg;
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/* Read the control two register. */
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result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg);
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if (result == kStatus_Success)
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{
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data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
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if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
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{
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/* Full duplex. */
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*duplex = kPHY_FullDuplex;
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}
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else
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{
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/* Half duplex. */
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*duplex = kPHY_HalfDuplex;
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}
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data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
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if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
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{
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/* 100M speed. */
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*speed = kPHY_Speed100M;
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}
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else
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2018-05-17 14:43:02 +08:00
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{
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/* 10M speed. */
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2018-05-11 20:34:54 +08:00
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*speed = kPHY_Speed10M;
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}
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}
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return result;
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}
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