2022-11-10 22:22:48 +08:00
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/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fsdmmc_dma.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:49:31
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2023-05-11 10:25:21 +08:00
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* Description: This file is dma descriptor management API.
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2022-11-10 22:22:48 +08:00
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 zhugengyu 2021/12/2 init
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*/
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/***************************** Include Files *********************************/
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#include "fassert.h"
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#include "fio.h"
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#include "fdebug.h"
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#include "fsdmmc_hw.h"
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#include "fsdmmc.h"
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#include "fsdmmc_dma.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FSDMMC_DEBUG_TAG "FSDMMC-DMA"
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#define FSDMMC_ERROR(format, ...) FT_DEBUG_PRINT_E(FSDMMC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDMMC_WARN(format, ...) FT_DEBUG_PRINT_W(FSDMMC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDMMC_INFO(format, ...) FT_DEBUG_PRINT_I(FSDMMC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDMMC_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSDMMC_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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/*****************************************************************************/
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/**
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* @name: FSdmmcSetReadDMA
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* @msg: 设置读数据DMA配置
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* @return {*}
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* @param {uintptr} base_addr FSDMMC 控制器基地址
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* @param {uintptr} card_addr 读卡地址
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* @param {u32} blk_cnt 读卡的block数
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* @param {void} *buf_p 读卡的目的地址
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*/
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void FSdmmcSetReadDMA(uintptr base_addr, uintptr card_addr, u32 blk_cnt, void *buf_p)
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{
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FASSERT(buf_p);
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u32 dsth = UPPER_32_BITS((uintptr)buf_p); /* DMA传输目的地址--> sd read buf */
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u32 dstl = LOWER_32_BITS((uintptr)buf_p);
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u32 srch = UPPER_32_BITS((uintptr)card_addr); /* DMA传输源地址 --> sd card */
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u32 srcl = LOWER_32_BITS((uintptr)card_addr);
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FSDMMC_INFO("sd card: 0x%x:0x%x ==> mem space: 0x%x:0x%x",
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srch, srcl, dsth, dstl);
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2023-05-11 10:25:21 +08:00
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FSDMMC_INFO("Read %d blks from 0x%x", blk_cnt, card_addr);
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2022-11-10 22:22:48 +08:00
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/* DMA 复位 */
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FSDMMC_SET_BIT(base_addr, FSDMMC_SOFTWARE_RESET_REG_OFFSET, FSDMMC_SOFTWARE_RESET_BDRST);
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FSDMMC_CLR_BIT(base_addr, FSDMMC_SOFTWARE_RESET_REG_OFFSET, FSDMMC_SOFTWARE_RESET_BDRST);
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/* 设置传输块数目 */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_BLK_CNT_REG_OFFSET, blk_cnt);
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/* 清除状态寄存器 */
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FSdmmcClearErrorInterruptStatus(base_addr);
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FSdmmcClearBDInterruptStatus(base_addr);
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FSdmmcClearNormalInterruptStatus(base_addr);
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2023-05-11 10:25:21 +08:00
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FSDMMC_INFO("Base addr: 0x%x buf_p: %p", base_addr, buf_p);
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FSDMMC_DATA_BARRIER();
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2022-11-10 22:22:48 +08:00
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/* DMA 读卡地址配置:4 个 cycle
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系统低 4B-系统高 4B-SD 低 4B- SD 高 4B */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_RX_BD_REG_OFFSET, dstl);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_RX_BD_REG_OFFSET, dsth);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_RX_BD_REG_OFFSET, srcl);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_RX_BD_REG_OFFSET, srch);
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FSDMMC_INFO("DMA READ START!");
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return;
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}
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/**
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* @name: FSdmmcSetWriteDMA
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* @msg: 设置写数据DMA配置
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* @return {*}
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* @param {uintptr} base_addr FSDMMC 控制器基地址
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* @param {uintptr} card_addr 写卡地址
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* @param {u32} blk_cnt 写卡的block数
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* @param {void} *buf_p 写卡的源地址
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*/
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void FSdmmcSetWriteDMA(uintptr base_addr, uintptr card_addr, u32 blk_cnt, const void *buf_p)
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{
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FASSERT(buf_p);
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u32 srch = UPPER_32_BITS((uintptr)buf_p); /* DMA传输源地址--> sd read buf */
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u32 srcl = LOWER_32_BITS((uintptr)buf_p);
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u32 dsth = UPPER_32_BITS((uintptr)card_addr); /* DMA传输目的地址 --> sd card */
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u32 dstl = LOWER_32_BITS((uintptr)card_addr);
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FSDMMC_INFO("mem space: 0x%x:0x%x ==> sd card: 0x%x:0x%x",
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srch, srcl, dsth, dstl);
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2023-05-11 10:25:21 +08:00
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FSDMMC_INFO("Write %d blks from 0x%x", blk_cnt, card_addr);
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2022-11-10 22:22:48 +08:00
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/* DMA 复位 */
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FSDMMC_SET_BIT(base_addr, FSDMMC_SOFTWARE_RESET_REG_OFFSET, FSDMMC_SOFTWARE_RESET_BDRST);
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FSDMMC_CLR_BIT(base_addr, FSDMMC_SOFTWARE_RESET_REG_OFFSET, FSDMMC_SOFTWARE_RESET_BDRST);
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/* 设置传输块数目 */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_BLK_CNT_REG_OFFSET, blk_cnt);
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/* 清除状态寄存器 */
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FSdmmcClearErrorInterruptStatus(base_addr);
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FSdmmcClearBDInterruptStatus(base_addr);
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FSdmmcClearNormalInterruptStatus(base_addr);
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2023-05-11 10:25:21 +08:00
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FSDMMC_DATA_BARRIER();
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2022-11-10 22:22:48 +08:00
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/* DMA 写卡地址配置:4 个 cycle
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系统低 4B-系统高 4B-SD 低 4B- SD 高 4B */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_TX_BD_REG_OFFSET, srcl);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_TX_BD_REG_OFFSET, srch);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_TX_BD_REG_OFFSET, dstl);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_TX_BD_REG_OFFSET, dsth);
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FSDMMC_INFO("DMA WRITE START!");
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return;
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}
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