50 lines
1.8 KiB
C
50 lines
1.8 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-05 zylx The first version for STM32F4xx
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* 2019-4-25 misonyo port to IMXRT
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*/
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#ifndef SDRAM_PORT_H__
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#define SDRAM_PORT_H__
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/* parameters for sdram peripheral */
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#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U)
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/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */
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#define SDRAM_REGION kSEMC_SDRAM_CS0
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/* CS pin: kSEMC_MUXCSX0/1/2/3 */
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#define SDRAM_CS_PIN kSEMC_MUXCSX0
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/* size(kbyte):32MB = 32*1024*1KBytes */
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#define SDRAM_SIZE ((uint32_t)0x8000)
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/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
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#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit
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/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
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#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit
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/* cas latency clock number: kSEMC_LatencyOne/Two/Three */
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#define SDRAM_CAS_LATENCY kSEMC_LatencyThree
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/* Timing configuration for W9825G6KH */
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/* TRP:precharge to active command time (ns) */
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#define SDRAM_TRP 18
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/* TRCD:active to read/write command delay time (ns) */
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#define SDRAM_TRCD 18
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/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */
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#define SDRAM_REFRESH_RECOVERY 67
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/* TWR:write recovery time (ns). */
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#define SDRAM_TWR 12
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/* TRAS:active to precharge command time (ns). */
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#define SDRAM_TRAS 42
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/* TRC time (ns). */
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#define SDRAM_TRC 60
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/* active to active time (ns). */
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#define SDRAM_ACT2ACT 60
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/* refresh time (ns). 64ms */
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#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192
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#endif /* SDRAM_PORT_H__ */
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