2019-10-03 22:29:13 +08:00
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/*
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2023-01-09 10:20:16 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2019-10-03 22:29:13 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-11-06 SummerGift first version
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* 2019-01-03 zylx modify DMA support
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*/
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#ifndef __SPI_CONFIG_H__
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#define __SPI_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_SPI1
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#ifndef SPI1_BUS_CONFIG
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#define SPI1_BUS_CONFIG \
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{ \
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.Instance = SPI1, \
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.bus_name = "spi1", \
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2021-04-23 09:52:17 +08:00
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.irq_type = SPI1_IRQn, \
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2019-10-03 22:29:13 +08:00
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}
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#endif /* SPI1_BUS_CONFIG */
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#endif /* BSP_USING_SPI1 */
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2021-03-08 22:40:39 +08:00
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2019-10-03 22:29:13 +08:00
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#ifdef BSP_SPI1_TX_USING_DMA
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#ifndef SPI1_TX_DMA_CONFIG
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#define SPI1_TX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI1_TX_DMA_RCC, \
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.Instance = SPI1_TX_DMA_INSTANCE, \
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.channel = SPI1_TX_DMA_CHANNEL, \
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.dma_irq = SPI1_TX_DMA_IRQ, \
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}
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#endif /* SPI1_TX_DMA_CONFIG */
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#endif /* BSP_SPI1_TX_USING_DMA */
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#ifdef BSP_SPI1_RX_USING_DMA
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#ifndef SPI1_RX_DMA_CONFIG
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#define SPI1_RX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI1_RX_DMA_RCC, \
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.Instance = SPI1_RX_DMA_INSTANCE, \
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.channel = SPI1_RX_DMA_CHANNEL, \
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.dma_irq = SPI1_RX_DMA_IRQ, \
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}
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#endif /* SPI1_RX_DMA_CONFIG */
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#endif /* BSP_SPI1_RX_USING_DMA */
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#ifdef BSP_USING_SPI2
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#ifndef SPI2_BUS_CONFIG
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#define SPI2_BUS_CONFIG \
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{ \
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.Instance = SPI2, \
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.bus_name = "spi2", \
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2021-04-23 09:52:17 +08:00
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.irq_type = SPI2_IRQn, \
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2019-10-03 22:29:13 +08:00
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}
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#endif /* SPI2_BUS_CONFIG */
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#endif /* BSP_USING_SPI2 */
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2021-03-08 22:40:39 +08:00
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2019-10-03 22:29:13 +08:00
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#ifdef BSP_SPI2_TX_USING_DMA
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#ifndef SPI2_TX_DMA_CONFIG
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#define SPI2_TX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI2_TX_DMA_RCC, \
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.Instance = SPI2_TX_DMA_INSTANCE, \
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.channel = SPI2_TX_DMA_CHANNEL, \
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.dma_irq = SPI2_TX_DMA_IRQ, \
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}
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#endif /* SPI2_TX_DMA_CONFIG */
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#endif /* BSP_SPI2_TX_USING_DMA */
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#ifdef BSP_SPI2_RX_USING_DMA
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#ifndef SPI2_RX_DMA_CONFIG
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#define SPI2_RX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI2_RX_DMA_RCC, \
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.Instance = SPI2_RX_DMA_INSTANCE, \
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.channel = SPI2_RX_DMA_CHANNEL, \
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.dma_irq = SPI2_RX_DMA_IRQ, \
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}
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#endif /* SPI2_RX_DMA_CONFIG */
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#endif /* BSP_SPI2_RX_USING_DMA */
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#ifdef BSP_USING_SPI3
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#ifndef SPI3_BUS_CONFIG
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#define SPI3_BUS_CONFIG \
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{ \
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.Instance = SPI3, \
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.bus_name = "spi3", \
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2021-04-23 09:52:17 +08:00
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.irq_type = SPI3_IRQn, \
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2019-10-03 22:29:13 +08:00
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}
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#endif /* SPI3_BUS_CONFIG */
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#endif /* BSP_USING_SPI3 */
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2021-03-08 22:40:39 +08:00
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2019-10-03 22:29:13 +08:00
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#ifdef BSP_SPI3_TX_USING_DMA
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#ifndef SPI3_TX_DMA_CONFIG
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#define SPI3_TX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI3_TX_DMA_RCC, \
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.Instance = SPI3_TX_DMA_INSTANCE, \
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.channel = SPI3_TX_DMA_CHANNEL, \
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.dma_irq = SPI3_TX_DMA_IRQ, \
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}
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#endif /* SPI3_TX_DMA_CONFIG */
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#endif /* BSP_SPI3_TX_USING_DMA */
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#ifdef BSP_SPI3_RX_USING_DMA
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#ifndef SPI3_RX_DMA_CONFIG
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#define SPI3_RX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI3_RX_DMA_RCC, \
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.Instance = SPI3_RX_DMA_INSTANCE, \
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.channel = SPI3_RX_DMA_CHANNEL, \
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.dma_irq = SPI3_RX_DMA_IRQ, \
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}
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#endif /* SPI3_RX_DMA_CONFIG */
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#endif /* BSP_SPI3_RX_USING_DMA */
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#ifdef BSP_USING_SPI4
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#ifndef SPI4_BUS_CONFIG
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#define SPI4_BUS_CONFIG \
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{ \
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.Instance = SPI4, \
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.bus_name = "spi4", \
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2021-04-23 09:52:17 +08:00
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.irq_type = SPI4_IRQn, \
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2019-10-03 22:29:13 +08:00
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}
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#endif /* SPI4_BUS_CONFIG */
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#endif /* BSP_USING_SPI4 */
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2021-03-08 22:40:39 +08:00
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2019-10-03 22:29:13 +08:00
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#ifdef BSP_SPI4_TX_USING_DMA
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#ifndef SPI4_TX_DMA_CONFIG
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#define SPI4_TX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI4_TX_DMA_RCC, \
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.Instance = SPI4_TX_DMA_INSTANCE, \
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.channel = SPI4_TX_DMA_CHANNEL, \
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.dma_irq = SPI4_TX_DMA_IRQ, \
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}
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#endif /* SPI4_TX_DMA_CONFIG */
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#endif /* BSP_SPI4_TX_USING_DMA */
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#ifdef BSP_SPI4_RX_USING_DMA
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#ifndef SPI4_RX_DMA_CONFIG
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#define SPI4_RX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI4_RX_DMA_RCC, \
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.Instance = SPI4_RX_DMA_INSTANCE, \
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.channel = SPI4_RX_DMA_CHANNEL, \
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.dma_irq = SPI4_RX_DMA_IRQ, \
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}
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#endif /* SPI4_RX_DMA_CONFIG */
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#endif /* BSP_SPI4_RX_USING_DMA */
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#ifdef BSP_USING_SPI5
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#ifndef SPI5_BUS_CONFIG
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#define SPI5_BUS_CONFIG \
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{ \
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.Instance = SPI5, \
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.bus_name = "spi5", \
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2021-04-23 09:52:17 +08:00
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.irq_type = SPI5_IRQn, \
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2019-10-03 22:29:13 +08:00
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}
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#endif /* SPI5_BUS_CONFIG */
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#endif /* BSP_USING_SPI5 */
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2021-03-08 22:40:39 +08:00
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2019-10-03 22:29:13 +08:00
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#ifdef BSP_SPI5_TX_USING_DMA
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#ifndef SPI5_TX_DMA_CONFIG
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#define SPI5_TX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI5_TX_DMA_RCC, \
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.Instance = SPI5_TX_DMA_INSTANCE, \
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.channel = SPI5_TX_DMA_CHANNEL, \
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.dma_irq = SPI5_TX_DMA_IRQ, \
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}
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#endif /* SPI5_TX_DMA_CONFIG */
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#endif /* BSP_SPI5_TX_USING_DMA */
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#ifdef BSP_SPI5_RX_USING_DMA
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#ifndef SPI5_RX_DMA_CONFIG
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#define SPI5_RX_DMA_CONFIG \
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{ \
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.dma_rcc = SPI5_RX_DMA_RCC, \
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.Instance = SPI5_RX_DMA_INSTANCE, \
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.channel = SPI5_RX_DMA_CHANNEL, \
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.dma_irq = SPI5_RX_DMA_IRQ, \
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}
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#endif /* SPI5_RX_DMA_CONFIG */
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#endif /* BSP_SPI5_RX_USING_DMA */
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#ifdef __cplusplus
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}
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#endif
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#endif /*__SPI_CONFIG_H__ */
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