232 lines
6.4 KiB
C
232 lines
6.4 KiB
C
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_GPC_H_
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#define _FSL_GPC_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup gpc
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief GPC driver version 2.1.1. */
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#define FSL_GPC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
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/*@}*/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*******************************************************************************
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* API
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******************************************************************************/
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#if (defined(FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) && FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM)
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/*!
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* @brief Allow all the IRQ/Events within the charge of GPC.
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*
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* @param base GPC peripheral base address.
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*/
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static inline void GPC_AllowIRQs(GPC_Type *base)
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{
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base->CNTR &= ~GPC_CNTR_GPCIRQM_MASK; /* Events would not be masked. */
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}
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/*!
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* @brief Disallow all the IRQ/Events within the charge of GPC.
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*
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* @param base GPC peripheral base address.
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*/
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static inline void GPC_DisallowIRQs(GPC_Type *base)
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{
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base->CNTR |= GPC_CNTR_GPCIRQM_MASK; /* Mask all the events. */
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}
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#endif /* FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM */
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/*!
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* @brief Enable the IRQ.
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*
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* @param base GPC peripheral base address.
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* @param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
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*/
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void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId);
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/*!
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* @brief Disable the IRQ.
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*
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* @param base GPC peripheral base address.
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* @param irqId ID number of IRQ to be disabled, available range is 32-159. 0-31 is available in some platforms.
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*/
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void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId);
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/*!
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* @brief Get the IRQ/Event flag.
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*
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* @param base GPC peripheral base address.
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* @param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
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* @return Indicated IRQ/Event is asserted or not.
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*/
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bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId);
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#if (defined(FSL_FEATURE_GPC_HAS_CNTR_L2PGE) && FSL_FEATURE_GPC_HAS_CNTR_L2PGE)
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/*!
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* @brief L2 Cache Power Gate Enable
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*
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* This function configures the L2 cache if it will keep power when in low power mode.
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* When the L2 cache power is OFF, L2 cache will be power down once when CPU core is power down
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* and will be hardware invalidated automatically when CPU core is re-power up.
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* When the L2 cache power is ON, L2 cache will keep power on even if CPU core is power down and
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* will not be hardware invalidated.
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* When CPU core is re-power up, the default setting is OFF.
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*
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* @param base GPC peripheral base address.
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* @param enable Enable the request or not.
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*/
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static inline void GPC_RequestL2CachePowerDown(GPC_Type *base, bool enable)
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{
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if (enable)
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{
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base->CNTR |= GPC_CNTR_L2_PGE_MASK; /* OFF. */
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}
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else
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{
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base->CNTR &= ~GPC_CNTR_L2_PGE_MASK; /* ON. */
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}
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}
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#endif /* FSL_FEATURE_GPC_HAS_CNTR_L2PGE */
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#if (defined(FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) && FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE)
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/*!
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* @brief FLEXRAM PDRAM0 Power Gate Enable
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*
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* This function configures the FLEXRAM PDRAM0 if it will keep power when cpu core is power down.
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* When the PDRAM0 Power is 1, PDRAM0 will be power down once when CPU core is power down.
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* When the PDRAM0 Power is 0, PDRAM0 will keep power on even if CPU core is power down.
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* When CPU core is re-power up, the default setting is 1.
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*
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* @param base GPC peripheral base address.
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* @param enable Enable the request or not.
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*/
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static inline void GPC_RequestPdram0PowerDown(GPC_Type *base, bool enable)
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{
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if (enable)
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{
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base->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; /* OFF. */
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}
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else
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{
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base->CNTR &= ~GPC_CNTR_PDRAM0_PGE_MASK; /* ON. */
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}
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}
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#endif /* FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE */
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#if (defined(FSL_FEATURE_GPC_HAS_CNTR_VADC) && FSL_FEATURE_GPC_HAS_CNTR_VADC)
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/*!
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* @brief VADC power down.
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*
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* This function requests the VADC power down.
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*
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* @param base GPC peripheral base address.
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* @param enable Enable the request or not.
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*/
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static inline void GPC_RequestVADCPowerDown(GPC_Type *base, bool enable)
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{
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if (enable)
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{
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base->CNTR &= ~GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC power down. */
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}
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else
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{
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base->CNTR |= GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC not power down. */
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}
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}
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/*!
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* @brief Checks if the VADC is power off.
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*
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* @param base GPC peripheral base address.
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* @return Whether the VADC is power off or not.
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*/
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static inline bool GPC_GetVADCPowerDownFlag(GPC_Type *base)
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{
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return (GPC_CNTR_VADC_ANALOG_OFF_MASK == (GPC_CNTR_VADC_ANALOG_OFF_MASK & base->CNTR));
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}
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#endif /* FSL_FEATURE_GPC_HAS_CNTR_VADC */
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#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) && FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR)
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/*!
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* @brief Checks if the DVFS0 is requesting for frequency/voltage update.
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*
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* @param base GPC peripheral base address.
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* @return Whether the DVFS0 is requesting for frequency/voltage update.
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*/
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static inline bool GPC_HasDVFS0ChangeRequest(GPC_Type *base)
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{
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return (GPC_CNTR_DVFS0CR_MASK == (GPC_CNTR_DVFS0CR_MASK & base->CNTR));
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}
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#endif /* FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR */
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#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) && FSL_FEATURE_GPC_HAS_CNTR_DISPLAY)
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/*!
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* @brief Requests the display power switch sequence.
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*
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* @param base GPC peripheral base address.
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* @param enable Enable the power on sequence, or the power down sequence.
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*/
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static inline void GPC_RequestDisplayPowerOn(GPC_Type *base, bool enable)
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{
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if (enable)
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{
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base->CNTR |= GPC_CNTR_DISPLAY_PUP_REQ_MASK; /* Power on sequence. */
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}
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else
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{
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base->CNTR |= GPC_CNTR_DISPLAY_PDN_REQ_MASK; /* Power down sequence. */
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}
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}
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#endif /* FSL_FEATURE_GPC_HAS_CNTR_DISPLAY */
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/*!
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* @brief Requests the MEGA power switch sequence.
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*
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* @param base GPC peripheral base address.
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* @param enable Enable the power on sequence, or the power down sequence.
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*/
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static inline void GPC_RequestMEGAPowerOn(GPC_Type *base, bool enable)
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{
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if (enable)
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{
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base->CNTR |= GPC_CNTR_MEGA_PUP_REQ_MASK; /* Power on sequence. */
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}
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else
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{
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base->CNTR |= GPC_CNTR_MEGA_PDN_REQ_MASK; /* Power down sequence. */
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}
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}
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/*!
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* @}
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*/
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#if defined(__cplusplus)
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}
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#endif
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/*!
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* @}
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*/
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#endif /* _FSL_GPC_H_ */
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