rt-thread/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h

//##==============================================================================
//##=== This script is generate by genswconfig.pl from .\00_Phobos_Pinlist_20220315.xls
//##=== Generate Time stamp is : 2022-03-17 14:04:49
//##==============================================================================

#ifndef __CV180X_PINLIST_SWCONFIG_H__
#define __CV180X_PINLIST_SWCONFIG_H__

#define SD0_CLK__SDIO0_CLK 0
#define SD0_CLK__IIC1_SDA 1
#define SD0_CLK__SPI0_SCK 2
#define SD0_CLK__XGPIOA_7 3
#define SD0_CLK__PWM_15 5
#define SD0_CLK__EPHY_LNK_LED 6
#define SD0_CLK__DBG_0 7
#define SD0_CMD__SDIO0_CMD 0
#define SD0_CMD__IIC1_SCL 1
#define SD0_CMD__SPI0_SDO 2
#define SD0_CMD__XGPIOA_8 3
#define SD0_CMD__PWM_14 5
#define SD0_CMD__EPHY_SPD_LED 6
#define SD0_CMD__DBG_1 7
#define SD0_D0__SDIO0_D_0 0
#define SD0_D0__CAM_MCLK1 1
#define SD0_D0__SPI0_SDI 2
#define SD0_D0__XGPIOA_9 3
#define SD0_D0__UART3_TX 4
#define SD0_D0__PWM_13 5
#define SD0_D0__WG0_D0 6
#define SD0_D0__DBG_2 7
#define SD0_D1__SDIO0_D_1 0
#define SD0_D1__IIC1_SDA 1
#define SD0_D1__AUX0 2
#define SD0_D1__XGPIOA_10 3
#define SD0_D1__UART1_TX 4
#define SD0_D1__PWM_12 5
#define SD0_D1__WG0_D1 6
#define SD0_D1__DBG_3 7
#define SD0_D2__SDIO0_D_2 0
#define SD0_D2__IIC1_SCL 1
#define SD0_D2__AUX1 2
#define SD0_D2__XGPIOA_11 3
#define SD0_D2__UART1_RX 4
#define SD0_D2__PWM_11 5
#define SD0_D2__WG1_D0 6
#define SD0_D2__DBG_4 7
#define SD0_D3__SDIO0_D_3 0
#define SD0_D3__CAM_MCLK0 1
#define SD0_D3__SPI0_CS_X 2
#define SD0_D3__XGPIOA_12 3
#define SD0_D3__UART3_RX 4
#define SD0_D3__PWM_10 5
#define SD0_D3__WG1_D1 6
#define SD0_D3__DBG_5 7
#define SD0_CD__SDIO0_CD 0
#define SD0_CD__XGPIOA_13 3
#define SD0_PWR_EN__SDIO0_PWR_EN 0
#define SD0_PWR_EN__XGPIOA_14 3
#define SPK_EN__XGPIOA_15 3
#define UART0_TX__UART0_TX 0
#define UART0_TX__CAM_MCLK1 1
#define UART0_TX__PWM_4 2
#define UART0_TX__XGPIOA_16 3
#define UART0_TX__UART1_TX 4
#define UART0_TX__AUX1 5
#define UART0_TX__JTAG_TMS 6
#define UART0_TX__DBG_6 7
#define UART0_RX__UART0_RX 0
#define UART0_RX__CAM_MCLK0 1
#define UART0_RX__PWM_5 2
#define UART0_RX__XGPIOA_17 3
#define UART0_RX__UART1_RX 4
#define UART0_RX__AUX0 5
#define UART0_RX__JTAG_TCK 6
#define UART0_RX__DBG_7 7
#define SPINOR_HOLD_X__SPINOR_HOLD_X 1
#define SPINOR_HOLD_X__SPINAND_HOLD 2
#define SPINOR_HOLD_X__XGPIOA_26 3
#define SPINOR_SCK__SPINOR_SCK 1
#define SPINOR_SCK__SPINAND_CLK 2
#define SPINOR_SCK__XGPIOA_22 3
#define SPINOR_MOSI__SPINOR_MOSI 1
#define SPINOR_MOSI__SPINAND_MOSI 2
#define SPINOR_MOSI__XGPIOA_25 3
#define SPINOR_WP_X__SPINOR_WP_X 1
#define SPINOR_WP_X__SPINAND_WP 2
#define SPINOR_WP_X__XGPIOA_27 3
#define SPINOR_MISO__SPINOR_MISO 1
#define SPINOR_MISO__SPINAND_MISO 2
#define SPINOR_MISO__XGPIOA_23 3
#define SPINOR_CS_X__SPINOR_CS_X 1
#define SPINOR_CS_X__SPINAND_CS 2
#define SPINOR_CS_X__XGPIOA_24 3
#define JTAG_CPU_TMS__JTAG_TMS 0
#define JTAG_CPU_TMS__CAM_MCLK0 1
#define JTAG_CPU_TMS__PWM_7 2
#define JTAG_CPU_TMS__XGPIOA_19 3
#define JTAG_CPU_TMS__UART1_RTS 4
#define JTAG_CPU_TMS__AUX0 5
#define JTAG_CPU_TMS__UART1_TX 6
#define JTAG_CPU_TCK__JTAG_TCK 0
#define JTAG_CPU_TCK__CAM_MCLK1 1
#define JTAG_CPU_TCK__PWM_6 2
#define JTAG_CPU_TCK__XGPIOA_18 3
#define JTAG_CPU_TCK__UART1_CTS 4
#define JTAG_CPU_TCK__AUX1 5
#define JTAG_CPU_TCK__UART1_RX 6
#define IIC0_SCL__CV_SCL0__CR_4WTDI 0
#define IIC0_SDA__CV_SDA0__CR_4WTDO 0
#define IIC0_SCL__JTAG_TDI 0
#define IIC0_SCL__UART1_TX 1
#define IIC0_SCL__UART2_TX 2
#define IIC0_SCL__XGPIOA_28 3
#define IIC0_SCL__IIC0_SCL 4
#define IIC0_SCL__WG0_D0 5
#define IIC0_SCL__DBG_10 7
#define IIC0_SDA__JTAG_TDO 0
#define IIC0_SDA__UART1_RX 1
#define IIC0_SDA__UART2_RX 2
#define IIC0_SDA__XGPIOA_29 3
#define IIC0_SDA__IIC0_SDA 4
#define IIC0_SDA__WG0_D1 5
#define IIC0_SDA__WG1_D0 6
#define IIC0_SDA__DBG_11 7
#define AUX0__AUX0 0
#define AUX0__XGPIOA_30 3
#define AUX0__IIS1_MCLK 4
#define AUX0__WG1_D1 6
#define AUX0__DBG_12 7
#define GPIO_ZQ__PWR_GPIO_24 3
#define GPIO_ZQ__PWM_2 4
#define PWR_VBAT_DET__PWR_VBAT_DET 0
#define PWR_RSTN__PWR_RSTN 0
#define PWR_SEQ1__PWR_SEQ1 0
#define PWR_SEQ1__PWR_GPIO_3 3
#define PWR_SEQ2__PWR_SEQ2 0
#define PWR_SEQ2__PWR_GPIO_4 3
#define PTEST__PWR_PTEST 0
#define PWR_WAKEUP0__PWR_WAKEUP0 0
#define PWR_WAKEUP0__PWR_IR0 1
#define PWR_WAKEUP0__PWR_UART0_TX 2
#define PWR_WAKEUP0__PWR_GPIO_6 3
#define PWR_WAKEUP0__UART1_TX 4
#define PWR_WAKEUP0__IIC4_SCL 5
#define PWR_WAKEUP0__EPHY_LNK_LED 6
#define PWR_WAKEUP0__WG2_D0 7
#define PWR_BUTTON1__PWR_BUTTON1 0
#define PWR_BUTTON1__PWR_GPIO_8 3
#define PWR_BUTTON1__UART1_RX 4
#define PWR_BUTTON1__IIC4_SDA 5
#define PWR_BUTTON1__EPHY_SPD_LED 6
#define PWR_BUTTON1__WG2_D1 7
#define XTAL_XIN__PWR_XTAL_CLKIN 0
#define PWR_GPIO0__PWR_GPIO_0 0
#define PWR_GPIO0__UART2_TX 1
#define PWR_GPIO0__PWR_UART0_RX 2
#define PWR_GPIO0__PWM_8 4
#define PWR_GPIO1__PWR_GPIO_1 0
#define PWR_GPIO1__UART2_RX 1
#define PWR_GPIO1__EPHY_LNK_LED 3
#define PWR_GPIO1__PWM_9 4
#define PWR_GPIO1__PWR_IIC_SCL 5
#define PWR_GPIO1__IIC2_SCL 6
#define PWR_GPIO1__IIC0_SDA 7
#define PWR_GPIO2__PWR_GPIO_2 0
#define PWR_GPIO2__PWR_SECTICK 2
#define PWR_GPIO2__EPHY_SPD_LED 3
#define PWR_GPIO2__PWM_10 4
#define PWR_GPIO2__PWR_IIC_SDA 5
#define PWR_GPIO2__IIC2_SDA 6
#define PWR_GPIO2__IIC0_SCL 7
#define SD1_GPIO1__UART4_TX 1
#define SD1_GPIO1__PWR_GPIO_26 3
#define SD1_GPIO1__PWM_10 7
#define SD1_GPIO0__UART4_RX 1
#define SD1_GPIO0__PWR_GPIO_25 3
#define SD1_GPIO0__PWM_11 7
#define SD1_D3__PWR_SD1_D3 0
#define SD1_D3__SPI2_CS_X 1
#define SD1_D3__IIC1_SCL 2
#define SD1_D3__PWR_GPIO_18 3
#define SD1_D3__CAM_MCLK0 4
#define SD1_D3__UART3_CTS 5
#define SD1_D3__PWR_SPINOR1_CS_X 6
#define SD1_D3__PWM_4 7
#define SD1_D2__PWR_SD1_D2 0
#define SD1_D2__IIC1_SCL 1
#define SD1_D2__UART2_TX 2
#define SD1_D2__PWR_GPIO_19 3
#define SD1_D2__CAM_MCLK0 4
#define SD1_D2__UART3_TX 5
#define SD1_D2__PWR_SPINOR1_HOLD_X 6
#define SD1_D2__PWM_5 7
#define SD1_D1__PWR_SD1_D1 0
#define SD1_D1__IIC1_SDA 1
#define SD1_D1__UART2_RX 2
#define SD1_D1__PWR_GPIO_20 3
#define SD1_D1__CAM_MCLK1 4
#define SD1_D1__UART3_RX 5
#define SD1_D1__PWR_SPINOR1_WP_X 6
#define SD1_D1__PWM_6 7
#define SD1_D0__PWR_SD1_D0 0
#define SD1_D0__SPI2_SDI 1
#define SD1_D0__IIC1_SDA 2
#define SD1_D0__PWR_GPIO_21 3
#define SD1_D0__CAM_MCLK1 4
#define SD1_D0__UART3_RTS 5
#define SD1_D0__PWR_SPINOR1_MISO 6
#define SD1_D0__PWM_7 7
#define SD1_CMD__PWR_SD1_CMD 0
#define SD1_CMD__SPI2_SDO 1
#define SD1_CMD__IIC3_SCL 2
#define SD1_CMD__PWR_GPIO_22 3
#define SD1_CMD__CAM_VS0 4
#define SD1_CMD__EPHY_LNK_LED 5
#define SD1_CMD__PWR_SPINOR1_MOSI 6
#define SD1_CMD__PWM_8 7
#define SD1_CLK__PWR_SD1_CLK 0
#define SD1_CLK__SPI2_SCK 1
#define SD1_CLK__IIC3_SDA 2
#define SD1_CLK__PWR_GPIO_23 3
#define SD1_CLK__CAM_HS0 4
#define SD1_CLK__EPHY_SPD_LED 5
#define SD1_CLK__PWR_SPINOR1_SCK 6
#define SD1_CLK__PWM_9 7
#define PWM0_BUCK__PWM_0 0
#define PWM0_BUCK__XGPIOB_0 3
#define ADC1__XGPIOB_3 3
#define ADC1__KEY_COL2 4
#define ADC1__PWM_3 6
#define USB_VBUS_DET__USB_VBUS_DET 0
#define USB_VBUS_DET__XGPIOB_6 3
#define USB_VBUS_DET__CAM_MCLK0 4
#define USB_VBUS_DET__CAM_MCLK1 5
#define USB_VBUS_DET__PWM_4 6
#define MUX_SPI1_MISO__UART3_RTS 1
#define MUX_SPI1_MISO__IIC1_SDA 2
#define MUX_SPI1_MISO__XGPIOB_8 3
#define MUX_SPI1_MISO__PWM_9 4
#define MUX_SPI1_MISO__KEY_COL1 5
#define MUX_SPI1_MISO__SPI1_SDI 6
#define MUX_SPI1_MISO__DBG_14 7
#define MUX_SPI1_MOSI__UART3_RX 1
#define MUX_SPI1_MOSI__IIC1_SCL 2
#define MUX_SPI1_MOSI__XGPIOB_7 3
#define MUX_SPI1_MOSI__PWM_8 4
#define MUX_SPI1_MOSI__KEY_COL0 5
#define MUX_SPI1_MOSI__SPI1_SDO 6
#define MUX_SPI1_MOSI__DBG_13 7
#define MUX_SPI1_CS__UART3_CTS 1
#define MUX_SPI1_CS__CAM_MCLK0 2
#define MUX_SPI1_CS__XGPIOB_10 3
#define MUX_SPI1_CS__PWM_11 4
#define MUX_SPI1_CS__KEY_ROW3 5
#define MUX_SPI1_CS__SPI1_CS_X 6
#define MUX_SPI1_CS__DBG_16 7
#define MUX_SPI1_SCK__UART3_TX 1
#define MUX_SPI1_SCK__CAM_MCLK1 2
#define MUX_SPI1_SCK__XGPIOB_9 3
#define MUX_SPI1_SCK__PWM_10 4
#define MUX_SPI1_SCK__KEY_ROW2 5
#define MUX_SPI1_SCK__SPI1_SCK 6
#define MUX_SPI1_SCK__DBG_15 7
#define PAD_ETH_TXP__UART3_RX 1
#define PAD_ETH_TXP__IIC1_SCL 2
#define PAD_ETH_TXP__XGPIOB_25 3
#define PAD_ETH_TXP__PWM_13 4
#define PAD_ETH_TXP__CAM_MCLK0 5
#define PAD_ETH_TXP__SPI1_SDO 6
#define PAD_ETH_TXP__IIS2_LRCK 7
#define PAD_ETH_TXM__UART3_RTS 1
#define PAD_ETH_TXM__IIC1_SDA 2
#define PAD_ETH_TXM__XGPIOB_24 3
#define PAD_ETH_TXM__PWM_12 4
#define PAD_ETH_TXM__CAM_MCLK1 5
#define PAD_ETH_TXM__SPI1_SDI 6
#define PAD_ETH_TXM__IIS2_BCLK 7
#define PAD_ETH_RXP__UART3_TX 1
#define PAD_ETH_RXP__CAM_MCLK1 2
#define PAD_ETH_RXP__XGPIOB_27 3
#define PAD_ETH_RXP__PWM_15 4
#define PAD_ETH_RXP__CAM_HS0 5
#define PAD_ETH_RXP__SPI1_SCK 6
#define PAD_ETH_RXP__IIS2_DO 7
#define PAD_ETH_RXM__UART3_CTS 1
#define PAD_ETH_RXM__CAM_MCLK0 2
#define PAD_ETH_RXM__XGPIOB_26 3
#define PAD_ETH_RXM__PWM_14 4
#define PAD_ETH_RXM__CAM_VS0 5
#define PAD_ETH_RXM__SPI1_CS_X 6
#define PAD_ETH_RXM__IIS2_DI 7
#define GPIO_RTX__VI0_D_15 1
#define GPIO_RTX__XGPIOB_23 3
#define GPIO_RTX__PWM_1 4
#define GPIO_RTX__CAM_MCLK0 5
#define GPIO_RTX__IIS2_MCLK 7
#define PAD_MIPIRX4N__VI0_CLK 1
#define PAD_MIPIRX4N__IIC0_SCL 2
#define PAD_MIPIRX4N__XGPIOC_2 3
#define PAD_MIPIRX4N__IIC1_SDA 4
#define PAD_MIPIRX4N__CAM_MCLK0 5
#define PAD_MIPIRX4N__KEY_ROW0 6
#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
#define PAD_MIPIRX4P__VI0_D_0 1
#define PAD_MIPIRX4P__IIC0_SDA 2
#define PAD_MIPIRX4P__XGPIOC_3 3
#define PAD_MIPIRX4P__IIC1_SCL 4
#define PAD_MIPIRX4P__CAM_MCLK1 5
#define PAD_MIPIRX4P__KEY_ROW1 6
#define PAD_MIPIRX4P__MUX_SPI1_CS 7
#define PAD_MIPIRX3N__VI0_D_1 1
#define PAD_MIPIRX3N__XGPIOC_4 3
#define PAD_MIPIRX3N__CAM_MCLK0 4
#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
#define PAD_MIPIRX3P__VI0_D_2 1
#define PAD_MIPIRX3P__XGPIOC_5 3
#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
#define PAD_MIPIRX2N__VI0_D_3 1
#define PAD_MIPIRX2N__XGPIOC_6 3
#define PAD_MIPIRX2N__IIC4_SCL 5
#define PAD_MIPIRX2N__DBG_6 7
#define PAD_MIPIRX2P__VI0_D_4 1
#define PAD_MIPIRX2P__XGPIOC_7 3
#define PAD_MIPIRX2P__IIC4_SDA 5
#define PAD_MIPIRX2P__DBG_7 7
#define PAD_MIPIRX1N__VI0_D_5 1
#define PAD_MIPIRX1N__XGPIOC_8 3
#define PAD_MIPIRX1N__KEY_ROW3 6
#define PAD_MIPIRX1N__DBG_8 7
#define PAD_MIPIRX1P__VI0_D_6 1
#define PAD_MIPIRX1P__XGPIOC_9 3
#define PAD_MIPIRX1P__IIC1_SDA 4
#define PAD_MIPIRX1P__KEY_ROW2 6
#define PAD_MIPIRX1P__DBG_9 7
#define PAD_MIPIRX0N__VI0_D_7 1
#define PAD_MIPIRX0N__XGPIOC_10 3
#define PAD_MIPIRX0N__IIC1_SCL 4
#define PAD_MIPIRX0N__CAM_MCLK1 5
#define PAD_MIPIRX0N__DBG_10 7
#define PAD_MIPIRX0P__VI0_D_8 1
#define PAD_MIPIRX0P__XGPIOC_11 3
#define PAD_MIPIRX0P__CAM_MCLK0 4
#define PAD_MIPIRX0P__DBG_11 7
#define PAD_MIPI_TXM2__VI0_D_13 1
#define PAD_MIPI_TXM2__IIC0_SDA 2
#define PAD_MIPI_TXM2__XGPIOC_16 3
#define PAD_MIPI_TXM2__IIC1_SDA 4
#define PAD_MIPI_TXM2__PWM_8 5
#define PAD_MIPI_TXM2__SPI0_SCK 6
#define PAD_MIPI_TXP2__VI0_D_14 1
#define PAD_MIPI_TXP2__IIC0_SCL 2
#define PAD_MIPI_TXP2__XGPIOC_17 3
#define PAD_MIPI_TXP2__IIC1_SCL 4
#define PAD_MIPI_TXP2__PWM_9 5
#define PAD_MIPI_TXP2__SPI0_CS_X 6
#define PAD_MIPI_TXP2__IIS1_MCLK 7
#define PAD_MIPI_TXM1__SPI3_SDO 0
#define PAD_MIPI_TXM1__VI0_D_11 1
#define PAD_MIPI_TXM1__IIS1_LRCK 2
#define PAD_MIPI_TXM1__XGPIOC_14 3
#define PAD_MIPI_TXM1__IIC2_SDA 4
#define PAD_MIPI_TXM1__PWM_10 5
#define PAD_MIPI_TXM1__SPI0_SDO 6
#define PAD_MIPI_TXM1__DBG_14 7
#define PAD_MIPI_TXP1__SPI3_SDI 0
#define PAD_MIPI_TXP1__VI0_D_12 1
#define PAD_MIPI_TXP1__IIS1_DO 2
#define PAD_MIPI_TXP1__XGPIOC_15 3
#define PAD_MIPI_TXP1__IIC2_SCL 4
#define PAD_MIPI_TXP1__PWM_11 5
#define PAD_MIPI_TXP1__SPI0_SDI 6
#define PAD_MIPI_TXP1__DBG_15 7
#define PAD_MIPI_TXM0__SPI3_SCK 0
#define PAD_MIPI_TXM0__VI0_D_9 1
#define PAD_MIPI_TXM0__IIS1_DI 2
#define PAD_MIPI_TXM0__XGPIOC_12 3
#define PAD_MIPI_TXM0__CAM_MCLK1 4
#define PAD_MIPI_TXM0__PWM_14 5
#define PAD_MIPI_TXM0__CAM_VS0 6
#define PAD_MIPI_TXM0__DBG_12 7
#define PAD_MIPI_TXP0__SPI3_CS_X 0
#define PAD_MIPI_TXP0__VI0_D_10 1
#define PAD_MIPI_TXP0__IIS1_BCLK 2
#define PAD_MIPI_TXP0__XGPIOC_13 3
#define PAD_MIPI_TXP0__CAM_MCLK0 4
#define PAD_MIPI_TXP0__PWM_15 5
#define PAD_MIPI_TXP0__CAM_HS0 6
#define PAD_MIPI_TXP0__DBG_13 7
#define PKG_TYPE0__PKG_TYPE0 0
#define PKG_TYPE1__PKG_TYPE1 0
#define PKG_TYPE2__PKG_TYPE2 0
#define PAD_AUD_AINL_MIC__XGPIOC_23 3
#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
#define PAD_AUD_AINR_MIC__XGPIOC_22 3
#define PAD_AUD_AINR_MIC__IIS1_DO 4
#define PAD_AUD_AINR_MIC__IIS2_DI 5
#define PAD_AUD_AINR_MIC__IIS1_DI 6
#define PAD_AUD_AOUTL__XGPIOC_25 3
#define PAD_AUD_AOUTL__IIS1_LRCK 4
#define PAD_AUD_AOUTL__IIS2_LRCK 5
#define PAD_AUD_AOUTR__XGPIOC_24 3
#define PAD_AUD_AOUTR__IIS1_DI 4
#define PAD_AUD_AOUTR__IIS2_DO 5
#define PAD_AUD_AOUTR__IIS1_DO 6

#endif /* __CV180X_PINLIST_SWCONFIG_H__ */