2021-05-18 09:57:25 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting implementation
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* 2018/12/27 Jesven Add SMP support
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* 2021/02/02 lizhirui Add userspace support
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*/
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#include "cpuport.h"
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2021-05-21 17:03:30 +08:00
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#ifdef RT_USING_SMP
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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/*
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* rt_base_t rt_hw_interrupt_disable(void);
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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#ifdef RISCV_S_MODE
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csrrci a0, sstatus, 2
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#else
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csrrci a0, mstatus, 8
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#endif
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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csrw SRC_XSTATUS, a0
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ret
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_to(rt_ubase_t to);
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* #endif
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* a0 --> to
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* a1 --> to_thread
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*/
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2021-05-18 09:57:25 +08:00
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LOAD sp, (a0)
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2021-05-21 17:03:30 +08:00
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#ifdef RT_USING_SMP
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mv a0, a1
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call rt_cpus_lock_status_restore
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#endif
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LOAD a0, 2 * REGBYTES(sp)
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csrw SRC_XSTATUS, a0
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j rt_hw_context_switch_exit
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2021-05-18 09:57:25 +08:00
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/*
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2021-05-21 17:03:30 +08:00
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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2021-05-18 09:57:25 +08:00
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* void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
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2021-05-21 17:03:30 +08:00
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* #endif
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2021-05-18 09:57:25 +08:00
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*
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* a0 --> from
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* a1 --> to
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2021-05-21 17:03:30 +08:00
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* a2 --> to_thread
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2021-05-18 09:57:25 +08:00
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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2021-05-21 17:03:30 +08:00
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/* saved from thread context
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* x1/ra -> sp(0)
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* x1/ra -> sp(1)
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* mstatus.mie -> sp(2)
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* x(i) -> sp(i-4)
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*/
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#ifdef ARCH_RISCV_FPU
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addi sp, sp, -32 * FREGBYTES
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FSTORE f0, 0 * FREGBYTES(sp)
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FSTORE f1, 1 * FREGBYTES(sp)
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FSTORE f2, 2 * FREGBYTES(sp)
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FSTORE f3, 3 * FREGBYTES(sp)
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FSTORE f4, 4 * FREGBYTES(sp)
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FSTORE f5, 5 * FREGBYTES(sp)
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FSTORE f6, 6 * FREGBYTES(sp)
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FSTORE f7, 7 * FREGBYTES(sp)
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FSTORE f8, 8 * FREGBYTES(sp)
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FSTORE f9, 9 * FREGBYTES(sp)
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FSTORE f10, 10 * FREGBYTES(sp)
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FSTORE f11, 11 * FREGBYTES(sp)
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FSTORE f12, 12 * FREGBYTES(sp)
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FSTORE f13, 13 * FREGBYTES(sp)
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FSTORE f14, 14 * FREGBYTES(sp)
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FSTORE f15, 15 * FREGBYTES(sp)
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FSTORE f16, 16 * FREGBYTES(sp)
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FSTORE f17, 17 * FREGBYTES(sp)
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FSTORE f18, 18 * FREGBYTES(sp)
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FSTORE f19, 19 * FREGBYTES(sp)
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FSTORE f20, 20 * FREGBYTES(sp)
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FSTORE f21, 21 * FREGBYTES(sp)
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FSTORE f22, 22 * FREGBYTES(sp)
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FSTORE f23, 23 * FREGBYTES(sp)
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FSTORE f24, 24 * FREGBYTES(sp)
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FSTORE f25, 25 * FREGBYTES(sp)
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FSTORE f26, 26 * FREGBYTES(sp)
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FSTORE f27, 27 * FREGBYTES(sp)
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FSTORE f28, 28 * FREGBYTES(sp)
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FSTORE f29, 29 * FREGBYTES(sp)
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FSTORE f30, 30 * FREGBYTES(sp)
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FSTORE f31, 31 * FREGBYTES(sp)
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#endif
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addi sp, sp, -32 * REGBYTES
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STORE sp, (a0)
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STORE x1, 0 * REGBYTES(sp)
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STORE x1, 1 * REGBYTES(sp)
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csrr a0, SRC_XSTATUS
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#ifdef RISCV_S_MODE
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andi a0, a0, 2
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beqz a0, save_spie
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li a0, 0x20
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save_spie:
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STORE a0, 2 * REGBYTES(sp)
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#else
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andi a0, a0, 8
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beqz a0, save_mpie
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li a0, 0x80
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save_mpie:
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STORE a0, 2 * REGBYTES(sp)
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#endif
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STORE x4, 4 * REGBYTES(sp)
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STORE x5, 5 * REGBYTES(sp)
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STORE x6, 6 * REGBYTES(sp)
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STORE x7, 7 * REGBYTES(sp)
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STORE x8, 8 * REGBYTES(sp)
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STORE x9, 9 * REGBYTES(sp)
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STORE x10, 10 * REGBYTES(sp)
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STORE x11, 11 * REGBYTES(sp)
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STORE x12, 12 * REGBYTES(sp)
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STORE x13, 13 * REGBYTES(sp)
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STORE x14, 14 * REGBYTES(sp)
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STORE x15, 15 * REGBYTES(sp)
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STORE x16, 16 * REGBYTES(sp)
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STORE x17, 17 * REGBYTES(sp)
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STORE x18, 18 * REGBYTES(sp)
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STORE x19, 19 * REGBYTES(sp)
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STORE x20, 20 * REGBYTES(sp)
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STORE x21, 21 * REGBYTES(sp)
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STORE x22, 22 * REGBYTES(sp)
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STORE x23, 23 * REGBYTES(sp)
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STORE x24, 24 * REGBYTES(sp)
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STORE x25, 25 * REGBYTES(sp)
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STORE x26, 26 * REGBYTES(sp)
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STORE x27, 27 * REGBYTES(sp)
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STORE x28, 28 * REGBYTES(sp)
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STORE x29, 29 * REGBYTES(sp)
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STORE x30, 30 * REGBYTES(sp)
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STORE x31, 31 * REGBYTES(sp)
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/* restore to thread context
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* sp(0) -> epc;
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* sp(1) -> ra;
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* sp(i) -> x(i+2)
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*/
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LOAD sp, (a1)
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#ifdef RT_USING_SMP
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mv a0, a2
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call rt_cpus_lock_status_restore
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#endif /*RT_USING_SMP*/
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j rt_hw_context_switch_exit
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#ifdef RT_USING_SMP
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/*
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* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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*
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* a0 --> context
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* a1 --> from
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* a2 --> to
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* a3 --> to_thread
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*/
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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STORE a0, 0(a1)
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LOAD sp, 0(a2)
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move a0, a3
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call rt_cpus_lock_status_restore
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j rt_hw_context_switch_exit
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#endif
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.global rt_hw_context_switch_exit
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rt_hw_context_switch_exit:
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#ifdef RT_USING_SMP
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#ifdef RT_USING_SIGNALS
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mv a0, sp
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csrr t0, mhartid
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/* switch interrupt stack of current cpu */
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la sp, __stack_start__
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addi t1, t0, 1
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li t2, __STACKSIZE__
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mul t1, t1, t2
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add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
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call rt_signal_check
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mv sp, a0
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#endif
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#endif
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/* resw ra to mepc */
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LOAD a0, 0 * REGBYTES(sp)
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csrw SRC_XEPC, a0
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LOAD x1, 1 * REGBYTES(sp)
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#ifdef RISCV_S_MODE
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li t0, 0x00000120
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csrw sstatus, t0
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LOAD a0, 2 * REGBYTES(sp)
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csrs sstatus, a0
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#else
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li t0, 0x00007800
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csrw mstatus, t0
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LOAD a0, 2 * REGBYTES(sp)
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csrs mstatus, a0
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#endif
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2021-05-18 09:57:25 +08:00
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2021-05-21 17:03:30 +08:00
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LOAD x4, 4 * REGBYTES(sp)
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LOAD x5, 5 * REGBYTES(sp)
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LOAD x6, 6 * REGBYTES(sp)
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LOAD x7, 7 * REGBYTES(sp)
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LOAD x8, 8 * REGBYTES(sp)
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LOAD x9, 9 * REGBYTES(sp)
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LOAD x10, 10 * REGBYTES(sp)
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LOAD x11, 11 * REGBYTES(sp)
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LOAD x12, 12 * REGBYTES(sp)
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LOAD x13, 13 * REGBYTES(sp)
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LOAD x14, 14 * REGBYTES(sp)
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LOAD x15, 15 * REGBYTES(sp)
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LOAD x16, 16 * REGBYTES(sp)
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LOAD x17, 17 * REGBYTES(sp)
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LOAD x18, 18 * REGBYTES(sp)
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LOAD x19, 19 * REGBYTES(sp)
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LOAD x20, 20 * REGBYTES(sp)
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LOAD x21, 21 * REGBYTES(sp)
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LOAD x22, 22 * REGBYTES(sp)
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LOAD x23, 23 * REGBYTES(sp)
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LOAD x24, 24 * REGBYTES(sp)
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LOAD x25, 25 * REGBYTES(sp)
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LOAD x26, 26 * REGBYTES(sp)
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LOAD x27, 27 * REGBYTES(sp)
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LOAD x28, 28 * REGBYTES(sp)
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LOAD x29, 29 * REGBYTES(sp)
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LOAD x30, 30 * REGBYTES(sp)
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LOAD x31, 31 * REGBYTES(sp)
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2021-05-18 09:57:25 +08:00
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2021-05-21 17:03:30 +08:00
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addi sp, sp, 32 * REGBYTES
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2021-05-18 09:57:25 +08:00
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2021-05-21 17:03:30 +08:00
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#ifdef ARCH_RISCV_FPU
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FLOAD f0, 0 * FREGBYTES(sp)
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FLOAD f1, 1 * FREGBYTES(sp)
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FLOAD f2, 2 * FREGBYTES(sp)
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FLOAD f3, 3 * FREGBYTES(sp)
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FLOAD f4, 4 * FREGBYTES(sp)
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FLOAD f5, 5 * FREGBYTES(sp)
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FLOAD f6, 6 * FREGBYTES(sp)
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FLOAD f7, 7 * FREGBYTES(sp)
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FLOAD f8, 8 * FREGBYTES(sp)
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FLOAD f9, 9 * FREGBYTES(sp)
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FLOAD f10, 10 * FREGBYTES(sp)
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FLOAD f11, 11 * FREGBYTES(sp)
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FLOAD f12, 12 * FREGBYTES(sp)
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FLOAD f13, 13 * FREGBYTES(sp)
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FLOAD f14, 14 * FREGBYTES(sp)
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FLOAD f15, 15 * FREGBYTES(sp)
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FLOAD f16, 16 * FREGBYTES(sp)
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FLOAD f17, 17 * FREGBYTES(sp)
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FLOAD f18, 18 * FREGBYTES(sp)
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FLOAD f19, 19 * FREGBYTES(sp)
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FLOAD f20, 20 * FREGBYTES(sp)
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FLOAD f21, 21 * FREGBYTES(sp)
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FLOAD f22, 22 * FREGBYTES(sp)
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FLOAD f23, 23 * FREGBYTES(sp)
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FLOAD f24, 24 * FREGBYTES(sp)
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FLOAD f25, 25 * FREGBYTES(sp)
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FLOAD f26, 26 * FREGBYTES(sp)
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FLOAD f27, 27 * FREGBYTES(sp)
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FLOAD f28, 28 * FREGBYTES(sp)
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FLOAD f29, 29 * FREGBYTES(sp)
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FLOAD f30, 30 * FREGBYTES(sp)
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FLOAD f31, 31 * FREGBYTES(sp)
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2021-05-18 09:57:25 +08:00
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2021-05-21 17:03:30 +08:00
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addi sp, sp, 32 * FREGBYTES
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#endif
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2021-05-18 09:57:25 +08:00
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2021-05-21 17:03:30 +08:00
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XRET
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