2015-10-15 23:14:27 +08:00
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/*
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2018-10-22 11:02:14 +08:00
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* Copyright (c) 2006-2018, RT-Thread Development Team
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2015-10-15 23:14:27 +08:00
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*
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2018-10-22 11:02:14 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-10-15 23:14:27 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2013-05-19 Bernard The first version for LPC40xx
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*/
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#include "drv_sdram.h"
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#include <lpc_emc.h>
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#include <lpc_timer.h>
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#define SDRAM_BASE_ADDR 0xA0000000
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#define SDRAM_SIZE 0x2000000
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/*******************************************************************************************
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* @<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>sdram_gpio_config()
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* @<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD>void
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* @<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><EFBFBD>void
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* @<EFBFBD><EFBFBD><EFBFBD><EFBFBD> <EFBFBD><EFBFBD>SDRAM<EFBFBD>ܽ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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*********************************************************************************************/
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static void sdram_gpio_config(void)
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{
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LPC_IOCON->P3_0 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D0 @ P3.0 */
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LPC_IOCON->P3_1 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D1 @ P3.1 */
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LPC_IOCON->P3_2 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D2 @ P3.2 */
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LPC_IOCON->P3_3 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D3 @ P3.3 */
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LPC_IOCON->P3_4 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D4 @ P3.4 */
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LPC_IOCON->P3_5 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D5 @ P3.5 */
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LPC_IOCON->P3_6 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D6 @ P3.6 */
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LPC_IOCON->P3_7 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D7 @ P3.7 */
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LPC_IOCON->P3_8 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D8 @ P3.8 */
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LPC_IOCON->P3_9 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D9 @ P3.9 */
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LPC_IOCON->P3_10 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D10 @ P3.10 */
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LPC_IOCON->P3_11 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D11 @ P3.11 */
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LPC_IOCON->P3_12 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D12 @ P3.12 */
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LPC_IOCON->P3_13 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D13 @ P3.13 */
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LPC_IOCON->P3_14 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D14 @ P3.14 */
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LPC_IOCON->P3_15 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* D15 @ P3.15 */
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LPC_IOCON->P4_0 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A0 @ P4.0 */
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LPC_IOCON->P4_1 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A1 @ P4.1 */
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LPC_IOCON->P4_2 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A2 @ P4.2 */
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LPC_IOCON->P4_3 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A3 @ P4.3 */
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LPC_IOCON->P4_4 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A4 @ P4.4 */
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LPC_IOCON->P4_5 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A5 @ P4.5 */
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LPC_IOCON->P4_6 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A6 @ P4.6 */
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LPC_IOCON->P4_7 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A7 @ P4.7 */
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LPC_IOCON->P4_8 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A8 @ P4.8 */
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LPC_IOCON->P4_9 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A9 @ P4.9 */
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LPC_IOCON->P4_10 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A10 @ P4.10 */
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LPC_IOCON->P4_11 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A11 @ P4.11 */
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LPC_IOCON->P4_12 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A12 @ P4.12 */
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LPC_IOCON->P4_13 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A13 @ P4.13 */
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LPC_IOCON->P4_14 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* A14 @ P4.14 */
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LPC_IOCON->P4_25 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* WEN @ P4.25 */
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LPC_IOCON->P2_16 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* CASN @ P2.16 */
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LPC_IOCON->P2_17 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* RASN @ P2.17 */
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LPC_IOCON->P2_18 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* CLK[0] @ P2.18 */
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LPC_IOCON->P2_19 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* CLK[1] @ P2.19 */
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LPC_IOCON->P2_20 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* DYCSN[0] @ P2.20 */
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LPC_IOCON->P2_24 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* CKE[0] @ P2.24 */
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LPC_IOCON->P2_28 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* DQM[0] @ P2.28 */
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LPC_IOCON->P2_29 = (1 << 0 | 0 << 3 | 0 << 5 | 1 << 9); /* DQM[1] @ P2.29 */
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}
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void lpc_sdram_hw_init(void)
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{
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volatile uint32_t i;
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volatile uint32_t dwtemp;
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uint16_t wtemp = wtemp;
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TIM_TIMERCFG_Type TIM_ConfigStruct;
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TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_USVAL;
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TIM_ConfigStruct.PrescaleValue = 1;
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// Set configuration for Tim_config and Tim_MatchConfig
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TIM_Init(LPC_TIM0, TIM_TIMER_MODE, &TIM_ConfigStruct);
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LPC_SC->PCONP |= 0x00000800;
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LPC_SC->EMCDLYCTL = 0x00001010;
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LPC_EMC->Control = 0x00000001;
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LPC_EMC->Config = 0x00000000;
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sdram_gpio_config();
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//LPC_SC->EMCCLKSEL = 1; //<2F><><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>һ<EFBFBD><D2BB>Ƶ<EFBFBD>ʣ<EFBFBD>60Mhz
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LPC_EMC->DynamicRP = EMC_NS2CLK(20); /* 20ns, */
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LPC_EMC->DynamicRAS = /*EMC_NS2CLK(42, nsPerClk);*/ 15; /* 42ns to 100K ns, */
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LPC_EMC->DynamicSREX = 1 - 1; /* tSRE, 1clk, */
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LPC_EMC->DynamicAPR = 2 - 1; /* Not found!!! Estimated as 2clk, */
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LPC_EMC->DynamicDAL = EMC_NS2CLK(20) + 2; /* tDAL = tRP + tDPL = 20ns + 2clk */
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LPC_EMC->DynamicWR = 2 - 1; /* 2CLK, */
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LPC_EMC->DynamicRC = EMC_NS2CLK(63); /* H57V2562GTR-75C tRC=63ns(min)*/
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LPC_EMC->DynamicRFC = EMC_NS2CLK(63); /* H57V2562GTR-75C tRFC=tRC */
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LPC_EMC->DynamicXSR = 0x0000000F; /* exit self-refresh to active, <20><>֪<EFBFBD><D6AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD> */
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LPC_EMC->DynamicRRD = EMC_NS2CLK(63); /* 3clk, tRRD=15ns(min) */
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LPC_EMC->DynamicMRD = 2 - 1; /* 2clk, tMRD=2clk(min) */
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LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
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/* H57V2562GTR-75C: tCL=3CLK, tRCD=20ns(min), 3 CLK=24ns */
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LPC_EMC->DynamicRasCas0 = 0x303;
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/* For Manley lpc1778 SDRAM: H57V2562GTR-75C, 256Mb, 16Mx16, 4 banks, row=13, column=9 */
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#ifdef SDRAM_CONFIG_16BIT
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LPC_EMC->DynamicConfig0 = 0x680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
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#elif defined SDRAM_CONFIG_32BIT
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LPC_EMC->DynamicConfig0 = 0x4680; /* 256Mb, 16Mx16, 4 banks, row=13, column=9, RBC */
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#endif
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TIM_Waitms(100);
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LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
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TIM_Waitms(200); /* wait 200ms */
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LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
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LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
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for (i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
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LPC_EMC->DynamicRefresh = EMC_SDRAM_REFRESH(64);
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LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
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#ifdef SDRAM_CONFIG_16BIT
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wtemp = *((volatile uint16_t *)(SDRAM_BASE | (0x33 << 12))); /* 8 burst, 3 CAS latency */
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#elif defined SDRAM_CONFIG_32BIT
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dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x32 << 13))); /* 4 burst, 3 CAS latency */
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#endif
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LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */
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LPC_EMC->DynamicConfig0 |= 0x80000; /* enable buffer */
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TIM_Waitms(1);
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TIM_DeInit(LPC_TIM0);
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}
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