320 lines
14 KiB
C
320 lines
14 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file hal_dma.c
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/// @author AE TEAM
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/// @brief THIS FILE PROVIDES ALL THE DMA FIRMWARE FUNCTIONS.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#define _HAL_DMA_C_
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// Files includes
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#include "types.h"
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#include "hal_dma.h"
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup MM32_Hardware_Abstract_Layer
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup DMA_HAL
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @addtogroup DMA_Exported_Functions
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/// @{
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Deinitializes the DMA Channeln registers to their default reset
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/// values.
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/// @param select the DMA Channel.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void DMA_DeInit(DMA_Channel_TypeDef* channel)
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{
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channel->CCR &= ~DMA_CCR_EN;
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channel->CCR = 0;
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channel->CNDTR = 0;
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channel->CPAR = 0;
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channel->CMAR = 0;
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if((*(vu32*)&channel) >= (*(vu32*)DMA2_Channel1_BASE)) {
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DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
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}
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else {
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DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
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}
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Initializes the DMA Channeln according to the specified
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/// parameters in the init_struct.
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/// @param select the DMA Channel.
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/// @param init_struct: pointer to a DMA_InitTypeDef structure that
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/// contains the configuration information for the specified DMA
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/// Channel.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct)
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{
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MODIFY_REG(
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channel->CCR,
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(DMA_CCR_DIR | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL | DMA_CCR_M2M),
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((u32)init_struct->DMA_DIR | (u32)init_struct->DMA_Mode | (u32)init_struct->DMA_PeripheralInc |
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(u32)init_struct->DMA_MemoryInc | (u32)init_struct->DMA_PeripheralDataSize | (u32)init_struct->DMA_MemoryDataSize |
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(u32)init_struct->DMA_Priority | (u32)init_struct->DMA_M2M));
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MODIFY_REG(channel->CCR, DMA_CCR_ARE, init_struct->DMA_Auto_reload);
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channel->CNDTR = init_struct->DMA_BufferSize;
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channel->CPAR = init_struct->DMA_PeripheralBaseAddr;
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channel->CMAR = init_struct->DMA_MemoryBaseAddr;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Fills each init_struct member with its default value.
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/// @param init_struct : pointer to a DMA_InitTypeDef structure which will
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/// be initialized.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void DMA_StructInit(DMA_InitTypeDef* init_struct)
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{
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init_struct->DMA_PeripheralBaseAddr = 0;
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init_struct->DMA_MemoryBaseAddr = 0;
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init_struct->DMA_DIR = DMA_DIR_PeripheralSRC;
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init_struct->DMA_BufferSize = 0;
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init_struct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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init_struct->DMA_MemoryInc = DMA_MemoryInc_Disable;
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init_struct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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init_struct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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init_struct->DMA_Mode = DMA_Mode_Normal;
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init_struct->DMA_Priority = DMA_Priority_Low;
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init_struct->DMA_M2M = DMA_M2M_Disable;
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init_struct->DMA_Auto_reload = DMA_Auto_Reload_Disable;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Enables or disables the specified DMA Channeln.
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/// @param channel: select the DMA Channel.
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/// @param state: new state of the DMA Channeln.
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/// This parameter can be: ENABLE or DISABLE.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state)
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{
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MODIFY_REG(channel->CCR, DMA_CCR_EN, state << DMA_CCR_EN_Pos);
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Enables or disables the specified DMA Channeln interrupts.
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/// @param channel: select the DMA Channel.
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/// @param it: specifies the DMA interrupts sources to be enabled
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/// or disabled.
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/// This parameter can be any combination of the following values:
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/// @arg DMA_IT_TC: Transfer complete interrupt mask
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/// @arg DMA_IT_HT: Half transfer interrupt mask
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/// @arg DMA_IT_TE: Transfer error interrupt mask
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/// @param state: new state of the specified DMA interrupts.
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/// This parameter can be: ENABLE or DISABLE.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state)
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{
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(state) ? (channel->CCR |= it) : (channel->CCR &= ~it);
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Sets the number of data units in the select the DMA Channel .
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/// @param channel: select the DMA Channel
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/// @param DataNumber: The number of data units in the current DMAy Channelx
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/// transfer.
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/// @note This function can only be used when the DMAy_Channelx is disabled.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length)
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{
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channel->CNDTR = length;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Returns the number of remaining data units in the current
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/// DMA Channeln transfer.
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/// @param channel: select the DMA Channel.
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/// @retval The number of remaining data units in the current DMA Channeln
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/// transfer.
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////////////////////////////////////////////////////////////////////////////////
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u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel)
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{
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return channel->CNDTR;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Checks whether the specified DMA Channeln flag is set or not.
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/// @param flag: specifies the flag to check.
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/// This parameter can be one of the following values:
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/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
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/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
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/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
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/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
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/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
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/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
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/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
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/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
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/// @retval The new state of DMAy_FLAG (SET or RESET).
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////////////////////////////////////////////////////////////////////////////////
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FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag)
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{
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if(flag >= DMA2_FLAG_GL1 ) {
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return (DMA2->ISR & flag) ? SET : RESET;
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}
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return (DMA1->ISR & flag) ? SET : RESET;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Clears the DMA Channeln's pending flags.
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/// @param flag: specifies the flag to clear.
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/// This parameter can be any combination (for the same DMA) of the
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/// following values:
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/// @arg DMA1_FLAG_GLn: DMA1 Channeln global flag(n = 1..7).
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/// @arg DMA1_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..7).
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/// @arg DMA1_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..7).
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/// @arg DMA1_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..7).
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/// @arg DMA2_FLAG_GLn: DMA1 Channeln global flag(n = 1..5).
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/// @arg DMA2_FLAG_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
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/// @arg DMA2_FLAG_HTn: DMA1 Channeln half transfer flag(n = 1..5).
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/// @arg DMA2_FLAG_TEn: DMA1 Channeln transfer error flag(n = 1..5).
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void DMA_ClearFlag(DMA_Flags_TypeDef flag)
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{
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if(flag >= DMA2_FLAG_GL1 ) {
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DMA2->IFCR = flag;
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return ;
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}
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DMA1->IFCR = flag;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Checks whether the specified DMA Channeln interrupt has occurred or
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/// not.
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/// @param it: specifies the DMA interrupt source to check.
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/// This parameter can be one of the following values:
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/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
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/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
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/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
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/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
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/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
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/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
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/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
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/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
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/// @retval The new state of DMAy_IT (SET or RESET).
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////////////////////////////////////////////////////////////////////////////////
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ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it)
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{
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if(it >= DMA2_IT_GL1 ) {
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return (DMA2->ISR & it) ? SET : RESET;
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}
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return (DMA1->ISR & it) ? SET : RESET;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Clears the DMA Channeln's interrupt pending bits.
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/// @param it: specifies the DMA interrupt pending bit to clear.
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/// This parameter can be any combination (for the same DMA) of the
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/// following values:
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/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
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/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
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/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
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/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
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/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
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/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
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/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
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/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it)
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{
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if(it >= DMA2_IT_GL1 ) {
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DMA2->IFCR = it;
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return ;
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}
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DMA1->IFCR = it;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Set the DMA Channeln's Peripheral address.
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/// @param channel : where n can be 1 to 7 for DMA1 to select the DMA Channel.
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/// @param address : DMA Peripheral address.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 address)
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{
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channel->CPAR = address;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Set the DMA Channeln's Peripheral address.
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/// @param channel : select the DMA Channel.
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/// @param length : Transmit lengths.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 length)
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{
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channel->CNDTR = length;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Set the DMA Channeln's Peripheral address.
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/// @param channel :select the DMA Channel.
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/// @param address : DMA memery address.
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 address)
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{
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channel->CMAR = address;
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}
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////////////////////////////////////////////////////////////////////////////////
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/// @brief Clears the DMA Channeln's interrupt pending bits.
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/// @param it: specifies the DMA interrupt pending bit to clear.
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/// This parameter can be any combination (for the same DMA) of the
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/// following values:
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/// @arg DMA1_IT_GLn: DMA1 Channeln global interrupt(n = 1..7).
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/// @arg DMA1_IT_TCn: DMA1 Channeln transfer complete interrupt(n = 1..7).
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/// @arg DMA1_IT_HTn: DMA1 Channeln half transfer interrupt(n = 1..7).
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/// @arg DMA1_IT_TEn: DMA1 Channeln transfer error interrupt(n = 1..7).
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/// @arg DMA2_IT_GLn: DMA1 Channeln global flag(n = 1..5).
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/// @arg DMA2_IT_TCn: DMA1 Channeln transfer complete flag(n = 1..5).
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/// @arg DMA2_IT_HTn: DMA1 Channeln half transfer flag(n = 1..5).
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/// @arg DMA2_IT_TEn: DMA1 Channeln transfer error flag(n = 1..5).
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/// @retval None.
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////////////////////////////////////////////////////////////////////////////////
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void exDMA_ClearITPendingBit(DMA_Channel_TypeDef* channel, u32 it)
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{
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if(it >= DMA2_IT_GL1 ) {
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DMA2->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
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DMA2->IFCR = it;
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return ;
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}
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DMA1->IFCR |= (u32)0x0F << (((*(vu32*)&channel & (u32)0xff) - 8) / 5);
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DMA1->IFCR = it;
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}
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/// @}
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/// @}
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/// @}
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