165 lines
6.6 KiB
C
165 lines
6.6 KiB
C
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/*
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* File : mmu.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __MMU_H__
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#define __MMU_H__
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#include <rtthread.h>
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#define CACHE_LINE_SIZE 32
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/*
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* Hardware page table definitions.
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*
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* + Level 1 descriptor (PGD)
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* - common
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*/
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#define PGD_TYPE_MASK (3 << 0)
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#define PGD_TYPE_FAULT (0 << 0)
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#define PGD_TYPE_TABLE (1 << 0)
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#define PGD_TYPE_SECT (2 << 0)
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#define PGD_BIT4 (1 << 4)
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#define PGD_DOMAIN(x) ((x) << 5)
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#define PGD_PROTECTION (1 << 9) /* ARMv5 */
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/*
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* - section
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*/
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#define PGD_SECT_BUFFERABLE (1 << 2)
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#define PGD_SECT_CACHEABLE (1 << 3)
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#define PGD_SECT_XN (1 << 4) /* ARMv6 */
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#define PGD_SECT_AP0 (1 << 10)
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#define PGD_SECT_AP1 (1 << 11)
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#define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */
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#define PGD_SECT_APX (1 << 15) /* ARMv6 */
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#define PGD_SECT_S (1 << 16) /* ARMv6 */
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#define PGD_SECT_nG (1 << 17) /* ARMv6 */
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#define PGD_SECT_SUPER (1 << 18) /* ARMv6 */
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#define PGD_SECT_UNCACHED (0)
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#define PGD_SECT_BUFFERED (PGD_SECT_BUFFERABLE)
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#define PGD_SECT_WT (PGD_SECT_CACHEABLE)
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#define PGD_SECT_WB (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE)
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#define PGD_SECT_MINICACHE (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE)
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#define PGD_SECT_WBWA (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE)
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#define PGD_SECT_NONSHARED_DEV (PGD_SECT_TEX(2))
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/*
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* + Level 2 descriptor (PTE)
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* - common
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*/
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#define PTE_TYPE_MASK (3 << 0)
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#define PTE_TYPE_FAULT (0 << 0)
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#define PTE_TYPE_LARGE (1 << 0)
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#define PTE_TYPE_SMALL (2 << 0)
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#define PTE_TYPE_EXT (3 << 0) /* ARMv5 */
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#define PTE_BUFFERABLE (1 << 2)
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#define PTE_CACHEABLE (1 << 3)
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/*
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* - extended small page/tiny page
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*/
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#define PTE_EXT_XN (1 << 0) /* ARMv6 */
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#define PTE_EXT_AP_MASK (3 << 4)
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#define PTE_EXT_AP0 (1 << 4)
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#define PTE_EXT_AP1 (2 << 4)
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#define PTE_EXT_AP_UNO_SRO (0 << 4)
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#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
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#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
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#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
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#define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */
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#define PTE_EXT_APX (1 << 9) /* ARMv6 */
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#define PTE_EXT_SHARED (1 << 10) /* ARMv6 */
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#define PTE_EXT_NG (1 << 11) /* ARMv6 */
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/*
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* - small page
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*/
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#define PTE_SMALL_AP_MASK (0xff << 4)
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#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
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#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
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#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
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#define PTE_SMALL_AP_URW_SRW (0xff << 4)
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/*
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* sector table properities
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*/
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#define SECT_CB (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back
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#define SECT_CNB (PGD_SECT_CACHEABLE) //cache_on, write_through
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#define SECT_NCB (PGD_SECT_BUFFERABLE) //cache_off,WR_BUF on
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#define SECT_NCNB (0 << 2) //cache_off,WR_BUF off
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#define SECT_AP_RW (PGD_SECT_AP0|PGD_SECT_AP1) //supervisor=RW, user=RW
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#define SECT_AP_RO ((0 << 10)|(0 << 11)) //supervisor=RO, user=NO Access(SR=10)
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#define SECT_RW_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write back */
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#define SECT_RW_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write, cache, write through */
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#define SECT_RW_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */
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#define SECT_RW_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read/Write without cache and write buffer */
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#define SECT_RO_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write back */
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#define SECT_RO_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_BIT4) /* Read Only, cache, write through */
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#define SECT_RO_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */
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#define SECT_RO_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_BIT4) /* Read Only without cache and write buffer */
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#define SECT_TO_PAGE (PGD_DOMAIN(0)|PGD_TYPE_TABLE|PGD_BIT4) /* Level 2 descriptor (PTE) entry properity */
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/*
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* page table properities
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*/
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#define PAGE_CB (PTE_BUFFERABLE|PTE_CACHEABLE) //cache_on, write_back
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#define PAGE_CNB (PTE_CACHEABLE) //cache_on, write_through
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#define PAGE_NCB (PTE_BUFFERABLE) //cache_off,WR_BUF on
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#define PAGE_NCNB (0 << 2) //cache_off,WR_BUF off
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#define PAGE_AP_RW PTE_SMALL_AP_URW_SRW //supervisor=RW, user=RW
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#define PAGE_AP_RO PTE_SMALL_AP_UNO_SRO //supervisor=RO, user=NO Access(SR=10)
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#define PAGE_RW_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write, cache, write back */
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#define PAGE_RW_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write, cache, write through */
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#define PAGE_RW_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */
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#define PAGE_RW_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */
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#define PAGE_RO_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only, cache, write back */
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#define PAGE_RO_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only, cache, write through */
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#define PAGE_RO_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
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#define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
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struct mem_desc {
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rt_uint32_t vaddr_start;
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rt_uint32_t vaddr_end;
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rt_uint32_t paddr_start;
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rt_uint32_t sect_attr; /* when page mapped */
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rt_uint32_t page_attr; /* only sector mapped valid */
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rt_uint32_t mapped_mode;
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#define SECT_MAPPED 0
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#define PAGE_MAPPED 1
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};
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void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
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#endif
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