528 lines
17 KiB
C
528 lines
17 KiB
C
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/**
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* \file
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*
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* \brief SAM Control Area Network (CAN) Low Level Driver
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*
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* Copyright (C) 2015-2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#include "can.h"
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#include <string.h>
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/* Instance for GCLK setting. */
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struct system_gclk_chan_config gclk_chan_conf;
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/* Message ram definition. */
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COMPILER_ALIGNED(4)
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static struct can_rx_element_buffer can0_rx_buffer[CONF_CAN0_RX_BUFFER_NUM];
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COMPILER_ALIGNED(4)
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static struct can_rx_element_fifo_0 can0_rx_fifo_0[CONF_CAN0_RX_FIFO_0_NUM];
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COMPILER_ALIGNED(4)
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static struct can_rx_element_fifo_1 can0_rx_fifo_1[CONF_CAN0_RX_FIFO_1_NUM];
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COMPILER_ALIGNED(4)
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static struct can_tx_element can0_tx_buffer[CONF_CAN0_TX_BUFFER_NUM + CONF_CAN0_TX_FIFO_QUEUE_NUM];
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COMPILER_ALIGNED(4)
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static struct can_tx_event_element can0_tx_event_fifo[CONF_CAN0_TX_EVENT_FIFO];
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COMPILER_ALIGNED(4)
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static struct can_standard_message_filter_element can0_rx_standard_filter[CONF_CAN0_RX_STANDARD_ID_FILTER_NUM];
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COMPILER_ALIGNED(4)
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static struct can_extended_message_filter_element can0_rx_extended_filter[CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM];
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COMPILER_ALIGNED(4)
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static struct can_rx_element_buffer can1_rx_buffer[CONF_CAN1_RX_BUFFER_NUM];
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COMPILER_ALIGNED(4)
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static struct can_rx_element_fifo_0 can1_rx_fifo_0[CONF_CAN1_RX_FIFO_0_NUM];
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COMPILER_ALIGNED(4)
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static struct can_rx_element_fifo_1 can1_rx_fifo_1[CONF_CAN1_RX_FIFO_1_NUM];
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COMPILER_ALIGNED(4)
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static struct can_tx_element can1_tx_buffer[CONF_CAN1_TX_BUFFER_NUM + CONF_CAN1_TX_FIFO_QUEUE_NUM];
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COMPILER_ALIGNED(4)
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static struct can_tx_event_element can1_tx_event_fifo[CONF_CAN1_TX_EVENT_FIFO];
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COMPILER_ALIGNED(4)
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static struct can_standard_message_filter_element can1_rx_standard_filter[CONF_CAN1_RX_STANDARD_ID_FILTER_NUM];
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COMPILER_ALIGNED(4)
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static struct can_extended_message_filter_element can1_rx_extended_filter[CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM];
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static void _can_message_memory_init(Can *hw)
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{
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if (hw == CAN0) {
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hw->SIDFC.reg = CAN_SIDFC_FLSSA((uint32_t)can0_rx_standard_filter) |
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CAN_SIDFC_LSS(CONF_CAN0_RX_STANDARD_ID_FILTER_NUM);
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hw->XIDFC.reg = CAN_XIDFC_FLESA((uint32_t)can0_rx_extended_filter) |
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CAN_XIDFC_LSE(CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM);
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hw->RXF0C.reg = CAN_RXF0C_F0SA((uint32_t)can0_rx_fifo_0) |
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CAN_RXF0C_F0S(CONF_CAN0_RX_FIFO_0_NUM);
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hw->RXF1C.reg = CAN_RXF1C_F1SA((uint32_t)can0_rx_fifo_1) |
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CAN_RXF1C_F1S(CONF_CAN0_RX_FIFO_1_NUM);
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hw->RXBC.reg = CAN_RXBC_RBSA((uint32_t)can0_rx_buffer);
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hw->TXBC.reg = CAN_TXBC_TBSA((uint32_t)can0_tx_buffer) |
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CAN_TXBC_NDTB(CONF_CAN0_TX_BUFFER_NUM) |
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CAN_TXBC_TFQS(CONF_CAN0_TX_FIFO_QUEUE_NUM);
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hw->TXEFC.reg = CAN_TXEFC_EFSA((uint32_t)can0_tx_event_fifo) |
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CAN_TXEFC_EFS(CONF_CAN0_TX_EVENT_FIFO);
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} else if (hw == CAN1) {
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hw->SIDFC.reg = CAN_SIDFC_FLSSA((uint32_t)can1_rx_standard_filter) |
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CAN_SIDFC_LSS(CONF_CAN1_RX_STANDARD_ID_FILTER_NUM);
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hw->XIDFC.reg = CAN_XIDFC_FLESA((uint32_t)can1_rx_extended_filter) |
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CAN_XIDFC_LSE(CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM);
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hw->RXF0C.reg = CAN_RXF0C_F0SA((uint32_t)can1_rx_fifo_0) |
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CAN_RXF0C_F0S(CONF_CAN1_RX_FIFO_0_NUM);
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hw->RXF1C.reg = CAN_RXF1C_F1SA((uint32_t)can1_rx_fifo_1) |
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CAN_RXF1C_F1S(CONF_CAN1_RX_FIFO_1_NUM);
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hw->RXBC.reg = CAN_RXBC_RBSA((uint32_t)can1_rx_buffer);
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hw->TXBC.reg = CAN_TXBC_TBSA((uint32_t)can1_tx_buffer) |
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CAN_TXBC_NDTB(CONF_CAN1_TX_BUFFER_NUM) |
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CAN_TXBC_TFQS(CONF_CAN1_TX_FIFO_QUEUE_NUM);
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hw->TXEFC.reg = CAN_TXEFC_EFSA((uint32_t)can1_tx_event_fifo) |
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CAN_TXEFC_EFS(CONF_CAN1_TX_EVENT_FIFO);
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}
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/**
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* The data size in conf_can.h should be 8/12/16/20/24/32/48/64,
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* The corresponding setting value in register is 0/1//2/3/4/5/6/7.
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* To simplify the calculation, seperate to two group 8/12/16/20/24 which
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* increased with 4 and 32/48/64 which increased with 16.
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*/
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if (CONF_CAN_ELEMENT_DATA_SIZE <= 24) {
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hw->RXESC.reg = CAN_RXESC_RBDS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4) |
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CAN_RXESC_F0DS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4) |
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CAN_RXESC_F1DS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4);
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hw->TXESC.reg = CAN_TXESC_TBDS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4);
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} else {
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hw->RXESC.reg = CAN_RXESC_RBDS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
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CAN_RXESC_F0DS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
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CAN_RXESC_F1DS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
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hw->TXESC.reg = CAN_TXESC_TBDS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
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}
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}
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static void _can_set_configuration(Can *hw, struct can_config *config)
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{
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/* Timing setting. */
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hw->NBTP.reg = CAN_NBTP_NBRP(CONF_CAN_NBTP_NBRP_VALUE) |
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CAN_NBTP_NSJW(CONF_CAN_NBTP_NSJW_VALUE) |
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CAN_NBTP_NTSEG1(CONF_CAN_NBTP_NTSEG1_VALUE) |
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CAN_NBTP_NTSEG2(CONF_CAN_NBTP_NTSEG2_VALUE);
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hw->DBTP.reg = CAN_DBTP_DBRP(CONF_CAN_DBTP_DBRP_VALUE) |
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CAN_DBTP_DSJW(CONF_CAN_DBTP_DSJW_VALUE) |
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CAN_DBTP_DTSEG1(CONF_CAN_DBTP_DTSEG1_VALUE) |
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CAN_DBTP_DTSEG2(CONF_CAN_DBTP_DTSEG2_VALUE);
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if (config->tdc_enable) {
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hw->DBTP.reg |= CAN_DBTP_TDC;
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}
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if (config->run_in_standby) {
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hw->MRCFG.reg |= 0x01<<6;
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}
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hw->RWD.reg |= CAN_RWD_WDC(config->watchdog_configuration);
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if (config->transmit_pause) {
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hw->CCCR.reg |= CAN_CCCR_TXP;
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}
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if (config->edge_filtering) {
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hw->CCCR.reg |= CAN_CCCR_EFBI;
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}
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if (config->protocol_exception_handling) {
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hw->CCCR.reg |= CAN_CCCR_PXHD;
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}
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if (!config->automatic_retransmission) {
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hw->CCCR.reg |= CAN_CCCR_DAR;
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}
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if (config->clock_stop_request) {
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hw->CCCR.reg |= CAN_CCCR_CSR;
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}
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if (config->clock_stop_acknowledge) {
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hw->CCCR.reg |= CAN_CCCR_CSA;
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}
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hw->TSCC.reg = CAN_TSCC_TCP(config->timestamp_prescaler) |
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CAN_TSCC_TSS_INC_Val;
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hw->TOCC.reg = CAN_TOCC_TOP(config->timeout_period) |
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config->timeout_mode | config->timeout_enable;
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hw->TDCR.reg = CAN_TDCR_TDCO(config->delay_compensation_offset) |
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CAN_TDCR_TDCF(config->delay_compensation_filter_window_length);
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hw->GFC.reg = CAN_GFC_ANFS(config->nonmatching_frames_action_standard) |
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CAN_GFC_ANFE(config->nonmatching_frames_action_extended);
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if (config->remote_frames_standard_reject) {
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hw->GFC.reg |= CAN_GFC_RRFS;
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}
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if (config->remote_frames_extended_reject) {
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hw->GFC.reg |= CAN_GFC_RRFE;
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}
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hw->XIDAM.reg = config->extended_id_mask;
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if (config->rx_fifo_0_overwrite) {
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hw->RXF0C.reg |= CAN_RXF0C_F0OM;
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}
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hw->RXF0C.reg |= CAN_RXF0C_F0WM(config->rx_fifo_0_watermark);
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if (config->rx_fifo_1_overwrite) {
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hw->RXF1C.reg |= CAN_RXF1C_F1OM;
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}
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hw->RXF1C.reg |= CAN_RXF1C_F1WM(config->rx_fifo_1_watermark);
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if (config->tx_queue_mode) {
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hw->TXBC.reg |= CAN_TXBC_TFQM;
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}
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hw->TXEFC.reg |= CAN_TXEFC_EFWM(config->tx_event_fifo_watermark);
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}
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static void _can_enable_peripheral_clock(struct can_module *const module_inst)
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{
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if (module_inst->hw == CAN0) {
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/* Turn on the digital interface clock. */
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system_ahb_clock_set_mask(MCLK_AHBMASK_CAN0);
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} else if (module_inst->hw == CAN1) {
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/* Turn on the digital interface clock. */
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system_ahb_clock_set_mask(MCLK_AHBMASK_CAN1);
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}
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}
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void can_init(struct can_module *const module_inst, Can *hw,
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struct can_config *config)
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{
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/* Sanity check arguments */
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Assert(module_inst);
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Assert(hw);
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Assert(config);
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/* Associate the software module instance with the hardware module */
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module_inst->hw = hw;
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/* Enable peripheral clock */
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_can_enable_peripheral_clock(module_inst);
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/* Configure GCLK channel */
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system_gclk_chan_get_config_defaults(&gclk_chan_conf);
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gclk_chan_conf.source_generator = config->clock_source;
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if (hw == CAN0) {
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system_gclk_chan_set_config(CAN0_GCLK_ID, &gclk_chan_conf);
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system_gclk_chan_enable(CAN0_GCLK_ID);
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} else if (hw == CAN1) {
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system_gclk_chan_set_config(CAN1_GCLK_ID, &gclk_chan_conf);
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system_gclk_chan_enable(CAN1_GCLK_ID);
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}
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/* Configuration Change Enable. */
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hw->CCCR.reg |= CAN_CCCR_CCE;
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/* Initialize the message memory address. */
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_can_message_memory_init(hw);
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/* Set the configuration. */
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_can_set_configuration(hw, config);
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/* Enable the interrupt setting which no need change. */
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hw->ILE.reg = CAN_ILE_EINT0 | CAN_ILE_EINT1;
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hw->TXBTIE.reg = CAN_TXBTIE_MASK;
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hw->TXBCIE.reg = CAN_TXBCIE_MASK;
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}
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void can_set_baudrate(Can *hw, uint32_t baudrate)
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{
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uint32_t gclk_can_value = 0;
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uint32_t can_nbtp_nbrp_value;
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uint32_t can_nbtp_nsgw_value = 3, can_nbtp_ntseg1_value = 10, can_nbtp_ntseg2_value = 3;
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if (hw == CAN0) {
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gclk_can_value = system_gclk_chan_get_hz(CAN0_GCLK_ID);
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} else if (hw == CAN1) {
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gclk_can_value = system_gclk_chan_get_hz(CAN1_GCLK_ID);
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}
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can_nbtp_nbrp_value = gclk_can_value / baudrate / (3 + can_nbtp_ntseg1_value + can_nbtp_ntseg2_value);
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hw->NBTP.reg = CAN_NBTP_NBRP(can_nbtp_nbrp_value) |
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CAN_NBTP_NSJW(can_nbtp_nsgw_value) |
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CAN_NBTP_NTSEG1(can_nbtp_ntseg1_value) |
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CAN_NBTP_NTSEG2(can_nbtp_ntseg2_value);
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}
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void can_fd_set_baudrate(Can *hw, uint32_t baudrate)
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{
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uint32_t gclk_can_fd_value = 0;
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uint32_t can_fd_dbtp_dbrp_value;
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uint32_t can_fd_dbtp_dsgw_value = 3, can_fd_dbtp_dtseg1_value = 10, can_fd_dbtp_dtseg2_value = 3;
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if (hw == CAN0) {
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gclk_can_fd_value = system_gclk_chan_get_hz(CAN0_GCLK_ID);
|
||
|
|
} else if (hw == CAN1) {
|
||
|
|
gclk_can_fd_value = system_gclk_chan_get_hz(CAN1_GCLK_ID);
|
||
|
|
}
|
||
|
|
|
||
|
|
can_fd_dbtp_dbrp_value = gclk_can_fd_value / baudrate / (3 + can_fd_dbtp_dtseg1_value + can_fd_dbtp_dtseg2_value);
|
||
|
|
|
||
|
|
hw->NBTP.reg = CAN_DBTP_DBRP(can_fd_dbtp_dbrp_value) |
|
||
|
|
CAN_DBTP_DSJW(can_fd_dbtp_dsgw_value) |
|
||
|
|
CAN_DBTP_DTSEG1(can_fd_dbtp_dtseg1_value) |
|
||
|
|
CAN_DBTP_DTSEG2(can_fd_dbtp_dtseg2_value);
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_start(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg &= ~CAN_CCCR_INIT;
|
||
|
|
/* Wait for the sync. */
|
||
|
|
while (module_inst->hw->CCCR.reg & CAN_CCCR_INIT);
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_stop(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
|
||
|
|
/* Wait for the sync. */
|
||
|
|
while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_enable_fd_mode(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
|
||
|
|
/* Wait for the sync. */
|
||
|
|
while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
|
||
|
|
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_FDOE;
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_BRSE;
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_disable_fd_mode(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg &= ~CAN_CCCR_FDOE;
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_enable_restricted_operation_mode(
|
||
|
|
struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
|
||
|
|
/* Wait for the sync. */
|
||
|
|
while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
|
||
|
|
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_ASM;
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_disable_restricted_operation_mode(
|
||
|
|
struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg &= ~CAN_CCCR_ASM;
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_enable_bus_monitor_mode(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
|
||
|
|
/* Wait for the sync. */
|
||
|
|
while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
|
||
|
|
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_MON;
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_disable_bus_monitor_mode(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg &= ~CAN_CCCR_MON;
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_enable_sleep_mode(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_CSR;
|
||
|
|
/* Wait for the sync. */
|
||
|
|
while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
|
||
|
|
|
||
|
|
while (!(module_inst->hw->CCCR.reg & CAN_CCCR_CSA));
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_disable_sleep_mode(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
/* Enable peripheral clock */
|
||
|
|
_can_enable_peripheral_clock(module_inst);
|
||
|
|
if (module_inst->hw == CAN0) {
|
||
|
|
system_gclk_chan_set_config(CAN0_GCLK_ID, &gclk_chan_conf);
|
||
|
|
system_gclk_chan_enable(CAN0_GCLK_ID);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (module_inst->hw == CAN1) {
|
||
|
|
system_gclk_chan_set_config(CAN1_GCLK_ID, &gclk_chan_conf);
|
||
|
|
system_gclk_chan_enable(CAN1_GCLK_ID);
|
||
|
|
}
|
||
|
|
module_inst->hw->CCCR.reg &= CAN_CCCR_CSR;
|
||
|
|
while ((module_inst->hw->CCCR.reg & CAN_CCCR_CSA));
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_enable_test_mode(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
|
||
|
|
/* Wait for the sync. */
|
||
|
|
while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
|
||
|
|
|
||
|
|
module_inst->hw->CCCR.reg |= CAN_CCCR_TEST;
|
||
|
|
module_inst->hw->TEST.reg |= CAN_TEST_LBCK;
|
||
|
|
}
|
||
|
|
|
||
|
|
void can_disable_test_mode(struct can_module *const module_inst)
|
||
|
|
{
|
||
|
|
module_inst->hw->CCCR.reg &= ~CAN_CCCR_TEST;
|
||
|
|
}
|
||
|
|
|
||
|
|
enum status_code can_set_rx_standard_filter(
|
||
|
|
struct can_module *const module_inst,
|
||
|
|
struct can_standard_message_filter_element *sd_filter, uint32_t index)
|
||
|
|
{
|
||
|
|
if (module_inst->hw == CAN0) {
|
||
|
|
can0_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
|
||
|
|
return STATUS_OK;
|
||
|
|
} else if (module_inst->hw == CAN1) {
|
||
|
|
can1_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
return STATUS_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
enum status_code can_set_rx_extended_filter(
|
||
|
|
struct can_module *const module_inst,
|
||
|
|
struct can_extended_message_filter_element *et_filter, uint32_t index)
|
||
|
|
{
|
||
|
|
if (module_inst->hw == CAN0) {
|
||
|
|
can0_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
|
||
|
|
can0_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
|
||
|
|
return STATUS_OK;
|
||
|
|
} else if (module_inst->hw == CAN1) {
|
||
|
|
can1_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
|
||
|
|
can1_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
return STATUS_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
enum status_code can_get_rx_buffer_element(
|
||
|
|
struct can_module *const module_inst,
|
||
|
|
struct can_rx_element_buffer *rx_element, uint32_t index)
|
||
|
|
{
|
||
|
|
if (module_inst->hw == CAN0) {
|
||
|
|
memcpy(rx_element, &can0_rx_buffer[index], sizeof(struct can_rx_element_buffer));
|
||
|
|
return STATUS_OK;
|
||
|
|
} else if (module_inst->hw == CAN1) {
|
||
|
|
memcpy(rx_element, &can1_rx_buffer[index], sizeof(struct can_rx_element_buffer));
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
return STATUS_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
enum status_code can_get_rx_fifo_0_element(
|
||
|
|
struct can_module *const module_inst,
|
||
|
|
struct can_rx_element_fifo_0 *rx_element, uint32_t index)
|
||
|
|
{
|
||
|
|
if (module_inst->hw == CAN0) {
|
||
|
|
memcpy(rx_element, &can0_rx_fifo_0[index], sizeof(struct can_rx_element_buffer));
|
||
|
|
return STATUS_OK;
|
||
|
|
} else if (module_inst->hw == CAN1) {
|
||
|
|
memcpy(rx_element, &can1_rx_fifo_0[index], sizeof(struct can_rx_element_buffer));
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
return STATUS_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
enum status_code can_get_rx_fifo_1_element(
|
||
|
|
struct can_module *const module_inst,
|
||
|
|
struct can_rx_element_fifo_1 *rx_element, uint32_t index)
|
||
|
|
{
|
||
|
|
if (module_inst->hw == CAN0) {
|
||
|
|
memcpy(rx_element, &can0_rx_fifo_1[index], sizeof(struct can_rx_element_buffer));
|
||
|
|
return STATUS_OK;
|
||
|
|
} else if (module_inst->hw == CAN1) {
|
||
|
|
memcpy(rx_element, &can1_rx_fifo_1[index], sizeof(struct can_rx_element_buffer));
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
return STATUS_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
enum status_code can_set_tx_buffer_element(
|
||
|
|
struct can_module *const module_inst,
|
||
|
|
struct can_tx_element *tx_element, uint32_t index)
|
||
|
|
{
|
||
|
|
uint32_t i;
|
||
|
|
if (module_inst->hw == CAN0) {
|
||
|
|
can0_tx_buffer[index].T0.reg = tx_element->T0.reg;
|
||
|
|
can0_tx_buffer[index].T1.reg = tx_element->T1.reg;
|
||
|
|
for (i = 0; i < CONF_CAN_ELEMENT_DATA_SIZE; i++) {
|
||
|
|
can0_tx_buffer[index].data[i] = tx_element->data[i];
|
||
|
|
}
|
||
|
|
return STATUS_OK;
|
||
|
|
} else if (module_inst->hw == CAN1) {
|
||
|
|
can1_tx_buffer[index].T0.reg = tx_element->T0.reg;
|
||
|
|
can1_tx_buffer[index].T1.reg = tx_element->T1.reg;
|
||
|
|
for (i = 0; i < CONF_CAN_ELEMENT_DATA_SIZE; i++) {
|
||
|
|
can1_tx_buffer[index].data[i] = tx_element->data[i];
|
||
|
|
}
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
return STATUS_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|
||
|
|
enum status_code can_get_tx_event_fifo_element(
|
||
|
|
struct can_module *const module_inst,
|
||
|
|
struct can_tx_event_element *tx_event_element, uint32_t index)
|
||
|
|
{
|
||
|
|
if (module_inst->hw == CAN0) {
|
||
|
|
tx_event_element->E0.reg = can0_tx_event_fifo[index].E0.reg;
|
||
|
|
tx_event_element->E1.reg = can0_tx_event_fifo[index].E1.reg;
|
||
|
|
return STATUS_OK;
|
||
|
|
} else if (module_inst->hw == CAN1) {
|
||
|
|
tx_event_element->E0.reg = can1_tx_event_fifo[index].E0.reg;
|
||
|
|
tx_event_element->E1.reg = can1_tx_event_fifo[index].E1.reg;
|
||
|
|
return STATUS_OK;
|
||
|
|
}
|
||
|
|
return STATUS_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
|