529 lines
14 KiB
C
529 lines
14 KiB
C
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/*
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-10-30 CDT first version
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*/
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#include <board.h>
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#include <rtdbg.h>
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#ifdef RT_USING_PWM
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#if !defined(BSP_USING_PWM1) && !defined(BSP_USING_PWM2) && !defined(BSP_USING_PWM3) && \
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!defined(BSP_USING_PWM4) && !defined(BSP_USING_PWM5) && !defined(BSP_USING_PWM6) && \
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!defined(BSP_USING_PWM7) && !defined(BSP_USING_PWM8) && !defined(BSP_USING_PWM9) && \
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!defined(BSP_USING_PWM10) && !defined(BSP_USING_PWM11) && !defined(BSP_USING_PWM12)
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#error "Please define at least one BSP_USING_PWMx"
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/* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable PWM */
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#endif
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#define PWM_MAX_PERIOD (65535U)
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#define PWM_MIN_PERIOD (1U)
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#define PWM_MIN_PULSE (1U)
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#define PWM_MAX_CHANNEL (TMRA_CH_4)
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enum
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{
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#ifdef BSP_USING_PWM1
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PWM1_INDEX,
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#endif
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#ifdef BSP_USING_PWM2
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PWM2_INDEX,
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#endif
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#ifdef BSP_USING_PWM3
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PWM3_INDEX,
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#endif
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#ifdef BSP_USING_PWM4
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PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM6
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PWM6_INDEX,
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#endif
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#ifdef BSP_USING_PWM7
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PWM7_INDEX,
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#endif
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#ifdef BSP_USING_PWM8
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PWM8_INDEX,
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#endif
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#ifdef BSP_USING_PWM9
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PWM9_INDEX,
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#endif
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#ifdef BSP_USING_PWM10
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PWM10_INDEX,
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#endif
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#ifdef BSP_USING_PWM11
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PWM11_INDEX,
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#endif
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#ifdef BSP_USING_PWM12
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PWM12_INDEX,
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#endif
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};
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struct hc32_pwm_config
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{
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struct rt_device_pwm pwm_device;
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M4_TMRA_TypeDef *timer_periph;
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rt_uint8_t channel;
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char *name;
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};
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#ifndef HC32_PWM_CONFIG
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#define HC32_PWM_CONFIG(periph, ch, label) \
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{ \
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.timer_periph = periph, \
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.channel = ch, \
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.name = label \
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}
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#endif /* HC32_PWM_CONFIG */
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static struct hc32_pwm_config pwm_obj[] =
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{
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#ifdef BSP_USING_PWM1
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HC32_PWM_CONFIG(M4_TMRA_1 , 0, "pwm1"),
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#endif
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#ifdef BSP_USING_PWM2
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HC32_PWM_CONFIG(M4_TMRA_2 , 0, "pwm2"),
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#endif
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#ifdef BSP_USING_PWM3
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HC32_PWM_CONFIG(M4_TMRA_3 , 0, "pwm3"),
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#endif
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#ifdef BSP_USING_PWM4
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HC32_PWM_CONFIG(M4_TMRA_4 , 0, "pwm4"),
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#endif
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#ifdef BSP_USING_PWM5
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HC32_PWM_CONFIG(M4_TMRA_5 , 0, "pwm5"),
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#endif
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#ifdef BSP_USING_PWM6
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HC32_PWM_CONFIG(M4_TMRA_6 , 0, "pwm6"),
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#endif
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#ifdef BSP_USING_PWM7
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HC32_PWM_CONFIG(M4_TMRA_7 , 0, "pwm7"),
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#endif
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#ifdef BSP_USING_PWM8
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HC32_PWM_CONFIG(M4_TMRA_8 , 0, "pwm8"),
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#endif
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#ifdef BSP_USING_PWM9
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HC32_PWM_CONFIG(M4_TMRA_9 , 0, "pwm9"),
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#endif
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#ifdef BSP_USING_PWM10
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HC32_PWM_CONFIG(M4_TMRA_10 , 0, "pwm10"),
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#endif
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#ifdef BSP_USING_PWM11
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HC32_PWM_CONFIG(M4_TMRA_11 , 0, "pwm11"),
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#endif
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#ifdef BSP_USING_PWM12
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HC32_PWM_CONFIG(M4_TMRA_12 , 0, "pwm12"),
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#endif
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};
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static rt_uint16_t hc32_pwm_get_unit_number(M4_TMRA_TypeDef *TMRAx)
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{
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rt_uint16_t unit_num;
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const rt_uint32_t unit_step = 0x400U;
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if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)M4_TMRA_1))
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{
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unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_1)) / unit_step;
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}
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else
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{
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unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_5)) / unit_step + 4;
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}
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return unit_num;
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}
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static void hc32_pwm_clock_config(M4_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState)
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{
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rt_uint32_t timer_periph;
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rt_uint16_t unit_num;
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unit_num = hc32_pwm_get_unit_number(TMRAx);
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timer_periph = PWC_FCG2_TMRA_1 << unit_num;
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PWC_Fcg2PeriphClockCmd(timer_periph, enNewState);
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}
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static rt_err_t hc32_pwm_enable(M4_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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if (configuration->channel > PWM_MAX_CHANNEL)
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{
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return RT_EINVAL;
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}
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if (!enable)
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{
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TMRA_PWM_Cmd(TMRAx, configuration->channel, Disable);
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}
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else
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{
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TMRA_PWM_Cmd(TMRAx, configuration->channel, Enable);
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}
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return RT_EOK;
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}
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static rt_err_t hc32_pwm_get(M4_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration)
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{
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stc_clk_freq_t stcClkFreq;
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rt_uint32_t clk_freq;
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rt_uint16_t unit_num;
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rt_uint16_t div_val;
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CLK_GetClockFreq(&stcClkFreq);
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unit_num = hc32_pwm_get_unit_number(TMRAx);
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if (unit_num >= 4)
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{
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clk_freq = stcClkFreq.pclk1Freq;
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}
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else
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{
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clk_freq = stcClkFreq.pclk0Freq;
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}
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/* Convert nanosecond to frequency and duty cycle */
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div_val = 0x01 << (READ_REG32_BIT(TMRAx->BCSTR, TMRA_BCSTR_CKDIV) >> TMRA_BCSTR_CKDIV_POS);
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clk_freq /= 1000000UL;
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configuration->period = (TMRA_GetPeriodVal(TMRAx) + 1) * div_val * 1000UL / clk_freq;
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configuration->pulse = (TMRA_GetCmpVal(TMRAx, configuration->channel) + 1) * div_val * 1000UL / clk_freq;
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return RT_EOK;
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}
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static rt_err_t hc32_pwm_set(M4_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration)
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{
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rt_uint32_t period, pulse;
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rt_uint64_t clk_div;
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stc_clk_freq_t stcClkFreq;
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rt_uint32_t clk_freq;
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rt_uint16_t unit_num;
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rt_uint16_t div_val;
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CLK_GetClockFreq(&stcClkFreq);
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unit_num = hc32_pwm_get_unit_number(TMRAx);
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if (unit_num >= 4)
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{
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clk_freq = stcClkFreq.pclk1Freq;
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}
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else
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{
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clk_freq = stcClkFreq.pclk0Freq;
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}
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/* Convert nanosecond to frequency and duty cycle */
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clk_freq /= 1000000UL;
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period = (unsigned long long)configuration->period * clk_freq / 1000UL;
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clk_div = period / PWM_MAX_PERIOD + 1;
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if (clk_div > 1024)
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{
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return RT_EINVAL;
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}
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else if (clk_div != 1)
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{
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for (div_val=512; div_val>1; div_val>>=1)
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{
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if (clk_div > div_val)
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{
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clk_div = div_val << 1;
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break;
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}
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}
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}
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period = period / clk_div;
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TMRA_SetPCLKDiv(TMRAx, ((__CLZ(__RBIT(clk_div))) << TMRA_BCSTR_CKDIV_POS));
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if (period < PWM_MIN_PERIOD)
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{
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period = PWM_MIN_PERIOD;
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}
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TMRA_SetPeriodVal(TMRAx, period - 1);
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pulse = (unsigned long long)configuration->pulse * clk_freq / clk_div / 1000UL;
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if (pulse < PWM_MIN_PULSE)
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{
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pulse = PWM_MIN_PULSE;
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}
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else if (pulse > period)
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{
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pulse = period;
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}
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TMRA_SetCmpVal(TMRAx, configuration->channel, pulse - 1);
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TMRA_SetCntVal(TMRAx, 0);
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return RT_EOK;
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}
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static rt_err_t hc32_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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M4_TMRA_TypeDef *timer_periph = (M4_TMRA_TypeDef *)device->parent.user_data;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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return hc32_pwm_enable(timer_periph, configuration, RT_TRUE);
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case PWM_CMD_DISABLE:
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return hc32_pwm_enable(timer_periph, configuration, RT_FALSE);
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case PWM_CMD_SET:
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return hc32_pwm_set(timer_periph, configuration);
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case PWM_CMD_GET:
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return hc32_pwm_get(timer_periph, configuration);
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default:
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return RT_EINVAL;
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}
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}
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extern rt_err_t rt_hw_board_pwm_init(M4_TMRA_TypeDef *TMRAx);
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static rt_err_t hc32_pwm_init(struct hc32_pwm_config *device)
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{
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rt_err_t result = RT_EOK;
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stc_tmra_init_t stcTmraInit;
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stc_tmra_pwm_cfg_t stcPwmCfg;
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RT_ASSERT(device != RT_NULL);
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/* Enable Timer peripheral clock. */
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hc32_pwm_clock_config(device->timer_periph, Enable);
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/* pwm pin configuration */
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result = rt_hw_board_pwm_init(device->timer_periph);
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if (RT_EOK == result)
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{
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TMRA_DeInit(device->timer_periph);
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TMRA_StructInit(&stcTmraInit);
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stcTmraInit.u32PCLKDiv = TMRA_PCLK_DIV1;
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stcTmraInit.u32CntOvfOp = TMRA_OVF_CNT_CONTINUE;
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stcTmraInit.u32PeriodVal = 0xFFFF;
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stcTmraInit.u32CntVal = 0;
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TMRA_Init(device->timer_periph, &stcTmraInit);
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/* Set the comparison reference value */
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TMRA_PWM_StructInit(&stcPwmCfg);
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stcPwmCfg.u32StartPolarity = TMRA_PWM_START_HIGH;
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stcPwmCfg.u32StopPolarity = TMRA_PWM_STOP_LOW;
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stcPwmCfg.u32CmpPolarity = TMRA_PWM_CMP_LOW;
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stcPwmCfg.u32PeriodPolarity = TMRA_PWM_PERIOD_HIGH;
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/* config pwm channel */
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if (0 != (device->channel & 0x01))
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{
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TMRA_PWM_Config(device->timer_periph, TMRA_CH_1, &stcPwmCfg);
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TMRA_SetCmpVal(device->timer_periph, TMRA_CH_1, 0x7FFF);
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}
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if (0 != (device->channel & 0x02))
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{
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TMRA_PWM_Config(device->timer_periph, TMRA_CH_2, &stcPwmCfg);
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TMRA_SetCmpVal(device->timer_periph, TMRA_CH_2, 0x7FFF);
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}
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if (0 != (device->channel & 0x04))
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{
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TMRA_PWM_Config(device->timer_periph, TMRA_CH_3, &stcPwmCfg);
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TMRA_SetCmpVal(device->timer_periph, TMRA_CH_3, 0x7FFF);
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}
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if (0 != (device->channel & 0x08))
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{
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TMRA_PWM_Config(device->timer_periph, TMRA_CH_4, &stcPwmCfg);
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TMRA_SetCmpVal(device->timer_periph, TMRA_CH_4, 0x7FFF);
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}
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/* start timer */
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TMRA_Start(device->timer_periph);
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}
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return result;
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}
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static void hc32_pwm_get_channel(void)
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{
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#ifdef BSP_USING_PWM1_CH1
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pwm_obj[PWM1_INDEX].channel |= (0x01 << 0);
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#endif
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#ifdef BSP_USING_PWM1_CH2
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pwm_obj[PWM1_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM1_CH3
|
||
|
|
pwm_obj[PWM1_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM1_CH4
|
||
|
|
pwm_obj[PWM1_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM2_CH1
|
||
|
|
pwm_obj[PWM2_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM2_CH2
|
||
|
|
pwm_obj[PWM2_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM2_CH3
|
||
|
|
pwm_obj[PWM2_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM2_CH4
|
||
|
|
pwm_obj[PWM2_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM3_CH1
|
||
|
|
pwm_obj[PWM3_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM3_CH2
|
||
|
|
pwm_obj[PWM3_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM3_CH3
|
||
|
|
pwm_obj[PWM3_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM3_CH4
|
||
|
|
pwm_obj[PWM3_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM4_CH1
|
||
|
|
pwm_obj[PWM4_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM4_CH2
|
||
|
|
pwm_obj[PWM4_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM4_CH3
|
||
|
|
pwm_obj[PWM4_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM4_CH4
|
||
|
|
pwm_obj[PWM4_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM5_CH1
|
||
|
|
pwm_obj[PWM5_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM5_CH2
|
||
|
|
pwm_obj[PWM5_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM5_CH3
|
||
|
|
pwm_obj[PWM5_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM5_CH4
|
||
|
|
pwm_obj[PWM5_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM6_CH1
|
||
|
|
pwm_obj[PWM6_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM6_CH2
|
||
|
|
pwm_obj[PWM6_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM6_CH3
|
||
|
|
pwm_obj[PWM6_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM6_CH4
|
||
|
|
pwm_obj[PWM6_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM7_CH1
|
||
|
|
pwm_obj[PWM7_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM7_CH2
|
||
|
|
pwm_obj[PWM7_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM7_CH3
|
||
|
|
pwm_obj[PWM7_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM7_CH4
|
||
|
|
pwm_obj[PWM7_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM8_CH1
|
||
|
|
pwm_obj[PWM8_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM8_CH2
|
||
|
|
pwm_obj[PWM8_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM8_CH3
|
||
|
|
pwm_obj[PWM8_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM8_CH4
|
||
|
|
pwm_obj[PWM8_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM9_CH1
|
||
|
|
pwm_obj[PWM9_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM9_CH2
|
||
|
|
pwm_obj[PWM9_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM9_CH3
|
||
|
|
pwm_obj[PWM9_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM9_CH4
|
||
|
|
pwm_obj[PWM9_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM10_CH1
|
||
|
|
pwm_obj[PWM10_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM10_CH2
|
||
|
|
pwm_obj[PWM10_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM10_CH3
|
||
|
|
pwm_obj[PWM10_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM10_CH4
|
||
|
|
pwm_obj[PWM10_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM11_CH1
|
||
|
|
pwm_obj[PWM11_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM11_CH2
|
||
|
|
pwm_obj[PWM11_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM11_CH3
|
||
|
|
pwm_obj[PWM11_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM11_CH4
|
||
|
|
pwm_obj[PWM11_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM12_CH1
|
||
|
|
pwm_obj[PWM12_INDEX].channel |= (0x01 << 0);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM12_CH2
|
||
|
|
pwm_obj[PWM12_INDEX].channel |= (0x01 << 1);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM12_CH3
|
||
|
|
pwm_obj[PWM12_INDEX].channel |= (0x01 << 2);
|
||
|
|
#endif
|
||
|
|
#ifdef BSP_USING_PWM12_CH4
|
||
|
|
pwm_obj[PWM12_INDEX].channel |= (0x01 << 3);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct rt_pwm_ops pwm_ops =
|
||
|
|
{
|
||
|
|
.control = hc32_pwm_control
|
||
|
|
};
|
||
|
|
|
||
|
|
static int rt_hw_pwm_init(void)
|
||
|
|
{
|
||
|
|
int i = 0;
|
||
|
|
int result = RT_EOK;
|
||
|
|
|
||
|
|
hc32_pwm_get_channel();
|
||
|
|
for (i = 0; i < sizeof(pwm_obj) / sizeof(pwm_obj[0]); i++)
|
||
|
|
{
|
||
|
|
if (hc32_pwm_init(&pwm_obj[i]) != RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_E("%s init failed", pwm_obj[i].name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_D("%s init success", pwm_obj[i].name);
|
||
|
|
/* register pwm device */
|
||
|
|
if (rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].name, &pwm_ops, pwm_obj[i].timer_periph) == RT_EOK)
|
||
|
|
{
|
||
|
|
LOG_D("%s register success", pwm_obj[i].name);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_E("%s register failed", pwm_obj[i].name);
|
||
|
|
result = -RT_ERROR;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_pwm_init);
|
||
|
|
|
||
|
|
#endif /* RT_USING_PWM */
|