93 lines
5.0 KiB
C
93 lines
5.0 KiB
C
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/*!
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\file gd32f3x0_misc.h
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\brief definitions for the MISC
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F3X0_MISC_H
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#define GD32F3X0_MISC_H
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#include "gd32f3x0.h"
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/* constants definitions */
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/* set the RAM and FLASH base address */
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#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
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#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
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/* set the NVIC vector table offset mask */
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#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */
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/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
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#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */
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/* priority group - define the pre-emption priority and the subpriority */
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#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
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#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
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#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
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#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
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#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
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/* choose the method to enter or exit the lowpower mode */
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#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
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#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
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#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
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#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */
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#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */
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#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */
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/* choose the systick clock source */
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#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
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#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
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/* function declarations */
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/* set the priority group */
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void nvic_priority_group_set(uint32_t nvic_prigroup);
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/* enable NVIC request */
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void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
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/* disable NVIC request */
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void nvic_irq_disable(uint8_t nvic_irq);
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/* set the NVIC vector table base address */
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void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
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/* set the state of the low power mode */
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void system_lowpower_set(uint8_t lowpower_mode);
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/* reset the state of the low power mode */
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void system_lowpower_reset(uint8_t lowpower_mode);
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/* set the systick clock source */
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void systick_clksource_set(uint32_t systick_clksource);
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#endif /* GD32F3X0_MISC_H */
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