101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-30 lizhirui first version
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*/
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#ifndef __RISCV_MMU_H__
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#define __RISCV_MMU_H__
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#include <rtthread.h>
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#include <rthw.h>
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#include "riscv.h"
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#undef PAGE_SIZE
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#define PAGE_OFFSET_SHIFT 0
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#define PAGE_OFFSET_BIT 12
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#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT)
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#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
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#define VPN0_BIT 9
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#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT)
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#define VPN1_BIT 9
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#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT)
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#define VPN2_BIT 9
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#define PPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT)
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#define PPN0_BIT 9
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#define PPN1_SHIFT (PPN0_SHIFT + PPN0_BIT)
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#define PPN1_BIT 9
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#define PPN2_SHIFT (PPN1_SHIFT + PPN1_BIT)
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#define PPN2_BIT 26
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#define L1_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT + VPN1_BIT)
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#define L2_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT)
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#define L3_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT)
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#define ARCH_ADDRESS_WIDTH_BITS 64
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#define PHYSICAL_ADDRESS_WIDTH_BITS 56
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#define PAGE_ATTR_NEXT_LEVEL (0)
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#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
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#define PAGE_ATTR_READONLY (PTE_R)
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#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R)
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#define PAGE_ATTR_USER (PTE_U)
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#define PAGE_ATTR_SYSTEM (0)
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#define PAGE_DEFAULT_ATTR_LEAF (PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G)
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#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
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#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
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#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)
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/**
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* encoding of SATP (Supervisor Address Translation and Protection register)
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*/
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#define SATP_MODE_OFFSET 60
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#define SATP_MODE_BARE 0
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#define SATP_MODE_SV39 8
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#define SATP_MODE_SV48 9
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#define SATP_MODE_SV57 10
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#define SATP_MODE_SV64 11
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#define ARCH_VA_WIDTH 39
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#define SATP_MODE SATP_MODE_SV39
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#define mmu_flush_tlb() \
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do \
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{ \
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asm volatile("sfence.vma x0,x0"); \
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} while (0)
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#define MMU_MAP_K_DEVICE (PTE_G | PTE_W | PTE_R | PTE_V)
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#define MMU_MAP_K_RWCB (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
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#define MMU_MAP_U_RWCB (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
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#define MMU_MAP_U_RWCB_XN (PTE_U | PTE_W | PTE_R | PTE_V)
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#define MMU_MAP_U_RW (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
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#define PTE_XWR_MASK 0xe
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#define ARCH_PAGE_SIZE PAGE_SIZE
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#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1)
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#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT
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#define ARCH_INDEX_WIDTH 9
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#define ARCH_INDEX_SIZE (1ul << ARCH_INDEX_WIDTH)
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#define ARCH_INDEX_MASK (ARCH_INDEX_SIZE - 1)
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void mmu_set_pagetable(rt_ubase_t addr);
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void mmu_enable_user_page_access();
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void mmu_disable_user_page_access();
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#endif
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