342 lines
11 KiB
C
342 lines
11 KiB
C
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/**
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* \file
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*
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* \brief Global interrupt management for 32-bit AVR
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*
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* Copyright (c) 2010-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
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*/
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#ifndef UTILS_INTERRUPT_INTERRUPT_H
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#define UTILS_INTERRUPT_INTERRUPT_H
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#include <compiler.h>
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#include <preprocessor/tpaste.h>
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/**
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* \weakgroup interrupt_group
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*
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* @{
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*/
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//! Pointer to interrupt handler.
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#if (defined __GNUC__)
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typedef void (*__int_handler)(void);
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#elif (defined __ICCAVR32__)
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typedef void (__interrupt *__int_handler)(void);
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#endif
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/**
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* \name Interrupt Service Routine definition and registration
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*
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* @{
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*/
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#if defined(__GNUC__) || defined(__DOXYGEN__)
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/**
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* \brief Macro to declare an interrupt service routine
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*
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* With GCC, this macro only causes the function to be defined as an interrupt
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* service routine, i.e., it does not add any initialization code. A valid
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* function name is required for use with \ref irq_register_handler.
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*
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* With IAR, this macro defines the function as an interrupt service routine and
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* causes the compiler to add initialization code for the interrupt controller
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* (INTC). The interrupt group and level, as well as a valid function name are
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* therefore required.\n
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* \note If \ref CONFIG_INTERRUPT_FORCE_INTC is defined, only a valid function
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* name is required for use with \ref irq_register_handler. The initialization
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* code will be handled by the interrupt controller itself.
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*
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* Usage:
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* \code
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ISR(foo_irq_handler, AVR32_xxx_IRQ_GROUP, n)
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{
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// Function definition
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...
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}
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\endcode
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*
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* \param func Name for the function, needed by \ref irq_register_handler.
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* \param int_grp Interrupt group to define service routine for.
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* \param int_lvl Priority level to set for the interrupt group, in the range
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* \c 0 to \c 3.
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*
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* \note The interrupt groups can be found in the device header files for the
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* IAR toolchain (avr32/io\<part\>.h).
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*
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* \todo Update to use IRQ numbers when these are made available in the
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* device header files of both IAR and GCC.
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*/
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# define ISR(func, int_grp, int_lvl) \
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__attribute__((__interrupt__)) static void func (void)
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#elif defined(__ICCAVR32__) && defined(CONFIG_INTERRUPT_FORCE_INTC)
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# define ISR(func, int_grp, int_lvl) \
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__interrupt static void func (void)
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#elif defined(__ICCAVR32__)
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# define ISR0(...) _Pragma(#__VA_ARGS__)
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# define ISR(func, int_grp, int_lvl) \
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ISR0(handler=int_grp, int_lvl) \
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__interrupt static void func (void)
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#endif
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#if defined(__GNUC__) || defined(__DOXYGEN__) || defined(CONFIG_INTERRUPT_FORCE_INTC)
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# include <intc.h>
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/**
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* \brief Initialize interrupt vectors
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*
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* With GCC, this macro adds code for initialization of the interrupt vectors
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* with the driver for the interrupt controller (INTC).
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*
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* With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro
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* adds no code, since initialization of the INTC is handled by the compiler.
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* \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the
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* INTC driver, replacing the compiler built-in interrupt handler.
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*
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* This must be called prior to \ref irq_register_handler.
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*/
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# define irq_initialize_vectors() INTC_init_interrupts()
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/**
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* \brief Register handler for interrupt
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*
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* With GCC, this macro adds code for registering an interrupt handler with the
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* driver for the interrupt controller (INTC).
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*
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* With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro
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* adds no code, since initialization of the INTC is handled by the compiler.
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* \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the
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* INTC driver, replacing the compiler built-in interrupt handler.
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*
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* \param func Name of handler function to register for interrupt.
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* \param int_num Number of the interrupt line to register function for.
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* \param int_lvl Priority level to set for the interrupt's group, in the range
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* \c 0 to \c 3.
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*
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* Usage:
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* \code
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irq_initialize_vectors();
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irq_register_handler(foo_irq_handler, AVR32_xxx_IRQ, n);
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\endcode
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*
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* \note The function \a func must be defined with the \ref ISR macro.
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* \note The interrupt line number can be found in the device header files for
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* the GCC toolchain (avr32/\<part\>.h).
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*/
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# define irq_register_handler(func, int_num, int_lvl) \
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INTC_register_interrupt(func, int_num, \
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TPASTE2(AVR32_INTC_INT, int_lvl))
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#elif defined(__ICCAVR32__)
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# define irq_initialize_vectors() do{ } while(0)
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# define irq_register_handler(func, int_num, int_lvl) do{ } while(0)
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#endif
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//@}
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#if (defined __GNUC__)
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# define cpu_irq_enable() \
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do { \
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barrier(); \
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__builtin_csrf(AVR32_SR_GM_OFFSET); \
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} while (0)
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# define cpu_irq_disable() \
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do { \
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__builtin_ssrf(AVR32_SR_GM_OFFSET); \
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barrier(); \
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} while (0)
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#elif (defined __ICCAVR32__)
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# if (defined CONFIG_INTERRUPT_FORCE_INTC)
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# define cpu_irq_enable() \
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do { \
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barrier(); \
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__clear_status_flag(AVR32_SR_GM_OFFSET); \
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} while(0)
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# define cpu_irq_disable() \
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do { \
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__set_status_flag(AVR32_SR_GM_OFFSET); \
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barrier(); \
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} while (0)
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# else
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# define cpu_irq_enable() __enable_interrupt()
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# define cpu_irq_disable() __disable_interrupt()
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# endif
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#endif
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typedef uint32_t irqflags_t;
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static inline irqflags_t cpu_irq_save(void)
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{
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volatile irqflags_t flags;
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flags = sysreg_read(AVR32_SR);
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cpu_irq_disable();
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return flags;
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}
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static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
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{
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return !(flags & AVR32_SR_GM_MASK);
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}
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static inline void cpu_irq_restore(irqflags_t flags)
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{
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barrier();
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/* Restore the global IRQ mask status flag if it was previously set */
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if ( cpu_irq_is_enabled_flags(flags) ) {
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cpu_irq_enable();
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}
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barrier();
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}
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#define cpu_irq_is_enabled() cpu_irq_is_enabled_flags(sysreg_read(AVR32_SR))
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//! \name Global interrupt levels
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//@{
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/**
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* \brief Check if interrupt level is enabled in supplied flags
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*
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* \param flags State of interrupt flags.
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* \param level Bit position for interrupt level.
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*
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* \return True if interrupt level is enabled.
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*/
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static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
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uint32_t level)
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{
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return !(flags & (1 << level));
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}
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/**
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* \brief Check if interrupt level is enabled
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*
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* \param level Interrupt level (0 to 3).
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*
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* \return True if interrupt level \a level is enabled.
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*
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* \note The interrupt level must be known at compile time.
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*/
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#define cpu_irq_level_is_enabled(level) \
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cpu_irq_level_is_enabled_flags(sysreg_read(AVR32_SR), \
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TPASTE3(AVR32_SR_I, level, M_OFFSET))
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#if defined(__GNUC__) || defined(__DOXYGEN__)
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/**
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* \brief Enable interrupt level
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*
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* \param level Interrupt level to enable (0 to 3).
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*
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* \note The interrupt level must be known at compile time.
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*/
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# define cpu_irq_enable_level(level) \
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do { \
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barrier(); \
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__builtin_csrf(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \
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} while (0)
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/**
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* \brief Disable interrupt level
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*
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* \param level Interrupt level to disable (0 to 3).
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*
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* \note The interrupt level must be known at compile time.
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*/
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# define cpu_irq_disable_level(level) \
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do { \
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__builtin_ssrf(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \
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barrier(); \
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} while (0)
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#elif (defined __ICCAVR32__)
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# define cpu_irq_enable_level(level) \
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do { \
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barrier(); \
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__clear_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \
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} while(0)
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# define cpu_irq_disable_level(level) \
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do { \
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__set_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \
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barrier(); \
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} while (0)
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#endif
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//@}
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//@}
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/**
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* \weakgroup interrupt_deprecated_group
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* @{
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*/
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#define Enable_global_interrupt() cpu_irq_enable()
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#define Disable_global_interrupt() cpu_irq_disable()
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#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
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#define Enable_interrupt_level(level) cpu_irq_enable_level(level)
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#define Disable_interrupt_level(level) cpu_irq_disable_level(level)
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#define Is_interrupt_level_enabled(level) cpu_irq_level_is_enabled(level)
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/**
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* \name Interrupt protection of code sections
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* \note Use \ref cpu_irq_save and \ref cpu_irq_restore instead of these macros.
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* @{
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*/
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/**
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* \brief Start section with code protected against interrupts
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*/
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#define AVR32_ENTER_CRITICAL_REGION() \
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{ \
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bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
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Disable_global_interrupt();
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/**
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* \brief End section with code protected against interrupts
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*
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* \note This macro must always be used in conjunction with
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* \ref AVR32_ENTER_CRITICAL_REGION so that interrupts are enabled again.
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*/
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#define AVR32_LEAVE_CRITICAL_REGION() \
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if (global_interrupt_enabled) Enable_global_interrupt(); \
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}
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//@}
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//@}
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#endif /* UTILS_INTERRUPT_INTERRUPT_H */
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