369 lines
8.7 KiB
C
369 lines
8.7 KiB
C
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/*
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* Copyright 2014, General Dynamics C4 Systems
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*
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* This software may be distributed and modified according to the terms of
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* the GNU General Public License version 2. Note that NO WARRANTY is provided.
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* See "LICENSE_GPLv2.txt" for details.
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*
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* @TAG(GD_GPL)
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*/
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#include "gic_pl400.h"
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#include "iomap.h"
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#define BIT(n) (1ul<<(n))
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#define MASK(n) (BIT(n)-1ul)
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/* Setters/getters helpers */
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#define IRQ_REG(IRQ) ((IRQ) / 32)
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#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
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#define IRQ_MASK MASK(10)
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#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < SPECIAL_IRQ_START)
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#define CPU(X) (1<<(X))
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#define TARGET_CPU_ALLINT(CPU) ( \
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( ((CPU)&0xff)<<0 ) |\
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( ((CPU)&0xff)<<8 ) |\
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( ((CPU)&0xff)<<16 ) |\
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( ((CPU)&0xff)<<24 ) \
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)
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#define TARGET_CPU0_ALLINT TARGET_CPU_ALLINT(CPU(0))
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#define IRQ_SET_ALL 0xffffffff;
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/* Special IRQ's */
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#define SPECIAL_IRQ_START 1020
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#define IRQ_NONE 1023
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/* Memory map for GIC distributor */
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struct gic_dist_map {
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uint32_t enable; /* 0x000 */
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uint32_t ic_type; /* 0x004 */
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uint32_t dist_ident; /* 0x008 */
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uint32_t res1[29]; /* [0x00C, 0x080) */
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uint32_t group[32]; /* [0x080, 0x100) */
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uint32_t enable_set[32]; /* [0x100, 0x180) */
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uint32_t enable_clr[32]; /* [0x180, 0x200) */
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uint32_t pending_set[32]; /* [0x200, 0x280) */
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uint32_t pending_clr[32]; /* [0x280, 0x300) */
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uint32_t active[32]; /* [0x300, 0x380) */
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uint32_t active_clr[32]; /* [0x380, 0x400) */
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uint32_t priority[255]; /* [0x400, 0x7FC) */
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uint32_t res2; /* 0x7FC */
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uint32_t targets[255]; /* [0x800, 0xBFC) */
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uint32_t res3; /* 0xBFC */
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uint32_t config[64]; /* [0xC00, 0xD00) */
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uint32_t ppi_status; /* [0xD00, 0xD04) */
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uint32_t spi_status[15]; /* [0xD04, 0xD40) */
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uint32_t res4[112]; /* [0xD40, 0xF00) */
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uint32_t sgi_control; /* 0xF00 */
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uint32_t res5[3]; /* [0xF04, 0xF10) */
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uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */
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uint32_t sgi_pending_set[4]; /* [0xF20, 0xF30) */
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uint32_t res10[40]; /* [0xF30, 0xFD0) */
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uint32_t periph_id[8]; /* [0xFD0, 0xFF0) */
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uint32_t component_id[4]; /* [0xFF0, 0xFFF] */
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};
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/* Memory map for GIC cpu interface */
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struct gic_cpu_iface_map {
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uint32_t icontrol; /* 0x000 */
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uint32_t pri_msk_c; /* 0x004 */
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uint32_t bp_c; /* 0x008 */
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uint32_t int_ack; /* 0x00C */
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uint32_t eoi; /* 0x010 */
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uint32_t run_priority; /* 0x014 */
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uint32_t hi_pend; /* 0x018 */
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uint32_t ns_alias_bp_c; /* 0x01C */
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uint32_t ns_alias_ack; /* 0x020 GIC_PL400 only */
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uint32_t ns_alias_eoi; /* 0x024 GIC_PL400 only */
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uint32_t ns_alias_hi_pend; /* 0x028 GIC_PL400 only */
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uint32_t res1[41]; /* [0x02C, 0x0D0) */
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uint32_t active_priority[4]; /* [0x0D0, 0xC0] GIC_PL400 only */
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uint32_t ns_active_priority[4]; /* [0xE0,0xF0] GIC_PL400 only */
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uint32_t res4[3]; /* [0xF0, 0xFC] */
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uint32_t cpu_if_ident; /* 0x0FC */
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uint32_t deactive; /* [0x1000] */
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};
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volatile struct gic_dist_map *gic_dist =
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(volatile struct gic_dist_map*)(GIC_PL400_DISTRIBUTOR_PPTR);
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volatile struct gic_cpu_iface_map *gic_cpuiface =
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(volatile struct gic_cpu_iface_map*)(GIC_PL400_CONTROLLER_PPTR);
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/* Helpers */
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static inline int
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is_irq_pending(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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return !!(gic_dist->pending_set[word] & BIT(bit));
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}
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static inline int
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is_irq_active(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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return !!(gic_dist->active[word] & BIT(bit));
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}
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static inline int
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is_irq_enabled(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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return !!(gic_dist->enable_set[word] & BIT(bit));
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}
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static inline int
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is_irq_edge_triggered(irq_t irq)
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{
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int word = irq / 16;
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int bit = ((irq & 0xf) * 2);
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return !!(gic_dist->config[word] & BIT(bit + 1));
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}
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static inline int
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is_irq_1_N(irq_t irq)
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{
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int word = irq / 16;
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int bit = ((irq & 0xf) * 2);
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return !!(gic_dist->config[word] & BIT(bit + 0));
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}
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static inline int
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is_irq_N_N(irq_t irq)
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{
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return !(is_irq_1_N(irq));
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}
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static inline void
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dist_pending_clr(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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/* Using |= here is detrimental to your health */
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gic_dist->pending_clr[word] = BIT(bit);
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}
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static inline void
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dist_pending_set(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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gic_dist->pending_set[word] = BIT(bit);
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}
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static inline void
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dist_enable_clr(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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/* Using |= here is detrimental to your health */
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gic_dist->enable_clr[word] = BIT(bit);
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}
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static inline void
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dist_enable_set(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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gic_dist->enable_set[word] = BIT(bit);
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}
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/**
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DONT_TRANSLATE
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*/
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static void dist_init(void)
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{
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int i;
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int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
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gic_dist->enable = 0;
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#if 0
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/* configure to group 0 for security */
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for (i = 0; i < nirqs; i += 32) {
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gic_dist->group[i / 32] = 0xffffffff;
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}
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#endif
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for (i = 0; i < nirqs; i += 32) {
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/* disable */
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gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
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/* clear pending */
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gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
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}
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/* reset interrupts priority */
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for (i = 32; i < nirqs; i += 4) {
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gic_dist->priority[i / 4] = 0x0;
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}
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/*
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* reset int target to cpu 0
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* (Should really query which processor we're running on and use that)
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*/
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for (i = 0; i < nirqs; i += 4) {
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gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
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}
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/* level-triggered, 1-N */
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for (i = 64; i < nirqs; i += 32) {
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gic_dist->config[i / 32] = 0;
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//gic_dist->config[i / 32] = 0x55555555;
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}
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/* enable the int controller */
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gic_dist->enable = 1;
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}
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/**
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DONT_TRANSLATE
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*/
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static void cpu_iface_init(void)
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{
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uint32_t i;
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/* For non-Exynos4, the registers are banked per CPU, need to clear them */
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gic_dist->enable_clr[0] = IRQ_SET_ALL;
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gic_dist->pending_clr[0] = IRQ_SET_ALL;
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gic_dist->priority[0] = 0x00;
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/* put everything in group 0 */
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/* clear any software generated interrupts */
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for (i = 0; i < 16; i += 4) {
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gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
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}
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gic_cpuiface->icontrol = 0;
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gic_cpuiface->pri_msk_c = 0x000000f0;
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gic_cpuiface->bp_c = 0x00000003;
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while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != IRQ_NONE) {
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gic_cpuiface->eoi = i;
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}
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gic_cpuiface->icontrol = 0x1;
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}
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/**
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DONT_TRANSLATE
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*/
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void initIRQController(void)
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{
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dist_init();
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cpu_iface_init();
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}
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/*
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* The only sane way to get an GIC IRQ number that can be properly
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* ACKED later is through the int_ack register. Unfortunately, reading
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* this register changes the interrupt state to pending so future
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* reads will not return the same value For this reason, we have a
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* global variable to store the IRQ number.
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*/
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static uint32_t active_irq = IRQ_NONE;
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/**
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DONT_TRANSLATE
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*/
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interrupt_t
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getActiveIRQ(void)
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{
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uint32_t irq;
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if (!IS_IRQ_VALID(active_irq)) {
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active_irq = gic_cpuiface->int_ack;
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}
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if (IS_IRQ_VALID(active_irq)) {
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irq = active_irq & IRQ_MASK;
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} else {
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irq = 1023;
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}
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return irq;
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}
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/*
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* GIC has 4 states: pending->active(+pending)->inactive
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* seL4 expects two states: active->inactive.
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* We ignore the active state in GIC to conform
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*/
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/**
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DONT_TRANSLATE
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*/
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bool_t
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isIRQPending(void)
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{
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return IS_IRQ_VALID(gic_cpuiface->hi_pend);
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}
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/**
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DONT_TRANSLATE
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*/
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void
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maskInterrupt(bool_t disable, interrupt_t irq)
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{
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if (disable) {
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dist_enable_clr(irq);
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} else {
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dist_enable_set(irq);
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}
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}
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/**
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DONT_TRANSLATE
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*/
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void
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ackInterrupt(irq_t irq)
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{
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if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq)) {
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return;
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}
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if (is_irq_edge_triggered(irq)) {
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dist_pending_clr(irq);
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}
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gic_cpuiface->eoi = active_irq;
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active_irq = IRQ_NONE;
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}
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void
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handleSpuriousIRQ(void)
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{
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}
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void rt_hw_interrupt_mask(int vector)
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{
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maskInterrupt(1, vector);
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}
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void rt_hw_interrupt_umask(int vector)
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{
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maskInterrupt(0, vector);
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}
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int rt_hw_interrupt_get_irq(void)
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{
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return getActiveIRQ();
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}
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void rt_hw_interrupt_ack(int fiq_irq)
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{
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return ackInterrupt(fiq_irq);
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}
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