316 lines
9.9 KiB
C
316 lines
9.9 KiB
C
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/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the people's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SUN8IW19_CODEC_H
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#define _SUN8IW19_CODEC_H
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#define SUNXI_CODEC_BASE_ADDR (0x05096000)
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#define SUNXI_DAC_DPC 0x00
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#define SUNXI_DAC_FIFOC 0x10
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#define SUNXI_DAC_FIFOS 0x14
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#define SUNXI_DAC_TXDATA 0X20
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#define SUNXI_DAC_CNT 0x24
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#define SUNXI_DAC_DG 0x28
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#define SUNXI_ADC_FIFOC 0x30
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#define SUNXI_ADC_FIFOS 0x38
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#define SUNXI_ADC_RXDATA 0x40
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#define SUNXI_ADC_CNT 0x44
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#define SUNXI_ADC_DG 0x4C
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#define SUNXI_DAC_DAP_CTL 0xF0
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#define SUNXI_ADC_DAP_CTL 0xF8
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#define SUNXI_DAC_DRC_HHPFC 0x100
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#define SUNXI_DAC_DRC_LHPFC 0x104
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#define SUNXI_DAC_DRC_CTRL 0x108
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#define SUNXI_DAC_DRC_LPFHAT 0x10C
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#define SUNXI_DAC_DRC_LPFLAT 0x110
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#define SUNXI_DAC_DRC_RPFHAT 0x114
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#define SUNXI_DAC_DRC_RPFLAT 0x118
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#define SUNXI_DAC_DRC_LPFHRT 0x11C
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#define SUNXI_DAC_DRC_LPFLRT 0x120
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#define SUNXI_DAC_DRC_RPFHRT 0x124
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#define SUNXI_DAC_DRC_RPFLRT 0x128
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#define SUNXI_DAC_DRC_LRMSHAT 0x12C
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#define SUNXI_DAC_DRC_LRMSLAT 0x130
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#define SUNXI_DAC_DRC_RRMSHAT 0x134
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#define SUNXI_DAC_DRC_RRMSLAT 0x138
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#define SUNXI_DAC_DRC_HCT 0x13C
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#define SUNXI_DAC_DRC_LCT 0x140
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#define SUNXI_DAC_DRC_HKC 0x144
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#define SUNXI_DAC_DRC_LKC 0x148
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#define SUNXI_DAC_DRC_HOPC 0x14C
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#define SUNXI_DAC_DRC_LOPC 0x150
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#define SUNXI_DAC_DRC_HLT 0x154
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#define SUNXI_DAC_DRC_LLT 0x158
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#define SUNXI_DAC_DRC_HKI 0x15C
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#define SUNXI_DAC_DRC_LKI 0x160
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#define SUNXI_DAC_DRC_HOPL 0x164
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#define SUNXI_DAC_DRC_LOPL 0x168
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#define SUNXI_DAC_DRC_HET 0x16C
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#define SUNXI_DAC_DRC_LET 0x170
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#define SUNXI_DAC_DRC_HKE 0x174
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#define SUNXI_DAC_DRC_LKE 0x178
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#define SUNXI_DAC_DRC_HOPE 0x17C
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#define SUNXI_DAC_DRC_LOPE 0x180
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#define SUNXI_DAC_DRC_HKN 0x184
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#define SUNXI_DAC_DRC_LKN 0x188
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#define SUNXI_DAC_DRC_SFHAT 0x18C
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#define SUNXI_DAC_DRC_SFLAT 0x190
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#define SUNXI_DAC_DRC_SFHRT 0x194
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#define SUNXI_DAC_DRC_SFLRT 0x198
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#define SUNXI_DAC_DRC_MXGHS 0x19C
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#define SUNXI_DAC_DRC_MXGLS 0x1A0
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#define SUNXI_DAC_DRC_MNGHS 0x1A4
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#define SUNXI_DAC_DRC_MNGLS 0x1A8
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#define SUNXI_DAC_DRC_EPSHC 0x1AC
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#define SUNXI_DAC_DRC_EPSLC 0x1B0
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#define SUNXI_DAC_DRC_OPT 0x1B4
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#define SUNXI_DAC_DRC_HPFHGAIN 0x1B8
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#define SUNXI_DAC_DRC_HPFLGAIN 0x1BC
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#define SUNXI_ADC_DRC_HHPFC 0x200
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#define SUNXI_ADC_DRC_LHPFC 0x204
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#define SUNXI_ADC_DRC_CTRL 0x208
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#define SUNXI_ADC_DRC_LPFHAT 0x20C
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#define SUNXI_ADC_DRC_LPFLAT 0x210
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#define SUNXI_ADC_DRC_RPFHAT 0x214
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#define SUNXI_ADC_DRC_RPFLAT 0x218
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#define SUNXI_ADC_DRC_LPFHRT 0x21C
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#define SUNXI_ADC_DRC_LPFLRT 0x220
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#define SUNXI_ADC_DRC_RPFHRT 0x224
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#define SUNXI_ADC_DRC_RPFLRT 0x228
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#define SUNXI_ADC_DRC_LRMSHAT 0x22C
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#define SUNXI_ADC_DRC_LRMSLAT 0x230
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#define SUNXI_ADC_DRC_HCT 0x23C
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#define SUNXI_ADC_DRC_LCT 0x240
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#define SUNXI_ADC_DRC_HKC 0x244
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#define SUNXI_ADC_DRC_LKC 0x248
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#define SUNXI_ADC_DRC_HOPC 0x24C
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#define SUNXI_ADC_DRC_LOPC 0x250
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#define SUNXI_ADC_DRC_HLT 0x254
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#define SUNXI_ADC_DRC_LLT 0x258
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#define SUNXI_ADC_DRC_HKI 0x25C
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#define SUNXI_ADC_DRC_LKI 0x260
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#define SUNXI_ADC_DRC_HOPL 0x264
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#define SUNXI_ADC_DRC_LOPL 0x268
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#define SUNXI_ADC_DRC_HET 0x26C
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#define SUNXI_ADC_DRC_LET 0x270
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#define SUNXI_ADC_DRC_HKE 0x274
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#define SUNXI_ADC_DRC_LKE 0x278
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#define SUNXI_ADC_DRC_HOPE 0x27C
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#define SUNXI_ADC_DRC_LOPE 0x280
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#define SUNXI_ADC_DRC_HKN 0x284
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#define SUNXI_ADC_DRC_LKN 0x288
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#define SUNXI_ADC_DRC_SFHAT 0x28C
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#define SUNXI_ADC_DRC_SFLAT 0x290
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#define SUNXI_ADC_DRC_SFHRT 0x294
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#define SUNXI_ADC_DRC_SFLRT 0x298
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#define SUNXI_ADC_DRC_MXGHS 0x29C
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#define SUNXI_ADC_DRC_MXGLS 0x2A0
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#define SUNXI_ADC_DRC_MNGHS 0x2A4
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#define SUNXI_ADC_DRC_MNGLS 0x2A8
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#define SUNXI_ADC_DRC_EPSHC 0x2AC
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#define SUNXI_ADC_DRC_EPSLC 0x2B0
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#define SUNXI_ADC_DRC_OPT 0x2B4
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#define SUNXI_ADC_DRC_HPFHGAIN 0x2B8
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#define SUNXI_ADC_DRC_HPFLGAIN 0x2BC
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#define SUNXI_AC_VERSION 0x2C0
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/* Analog register base - Digital register base */
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/*SUNXI_PR_CFG is to tear the acreg and dcreg, it is of no real meaning*/
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#define SUNXI_PR_CFG (0x300)
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#define SUNXI_ADCL_ANA_CTL (SUNXI_PR_CFG + 0x00)
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#define SUNXI_DAC_ANA_CTL (SUNXI_PR_CFG + 0x10)
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#define SUNXI_MICBIAS_ANA_CTL (SUNXI_PR_CFG + 0x18)
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#define SUNXI_BIAS_ANA_CTL (SUNXI_PR_CFG + 0x20)
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/* SUNXI_DAC_DPC:0x00 */
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#define EN_DAC 31
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#define MODQU 25
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#define DWA_EN 24
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#define HPF_EN 18
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#define DVOL 12
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#define DAC_HUB_EN 0
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/* SUNXI_DAC_FIFOC:0x10 */
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#define DAC_FS 29
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#define FIR_VER 28
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#define SEND_LASAT 26
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#define FIFO_MODE 24
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#define DAC_DRQ_CLR_CNT 21
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#define TX_TRIG_LEVEL 8
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#define DAC_MONO_EN 6
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#define TX_SAMPLE_BITS 5
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#define DAC_DRQ_EN 4
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#define DAC_IRQ_EN 3
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#define FIFO_UNDERRUN_IRQ_EN 2
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#define FIFO_OVERRUN_IRQ_EN 1
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#define FIFO_FLUSH 0
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/* SUNXI_DAC_FIFOS:0x14 */
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#define TX_EMPTY 23
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#define DAC_TXE_CNT 8
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#define DAC_TXE_INT 3
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#define DAC_TXU_INT 2
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#define DAC_TXO_INT 1
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/* SUNXI_DAC_DG:0x28 */
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#define DAC_MODU_SEL 11
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#define DAC_PATTERN_SEL 9
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#define DAC_CODEC_CLK_SEL 8
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#define DAC_SWP 6
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#define ADDA_LOOP_MODE 0
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/* SUNXI_ADC_FIFOC:0x30 */
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#define ADC_FS 29
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#define EN_AD 28
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#define ADCFDT 26
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#define ADCDFEN 25
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#define RX_FIFO_MODE 24
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#define RX_SAMPLE_BITS 16
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#define ADC_CHAN_SEL 12
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#define RX_FIFO_TRG_LEVEL 4
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#define ADC_DRQ_EN 3
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#define ADC_IRQ_EN 2
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#define ADC_OVERRUN_IRQ_EN 1
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#define ADC_FIFO_FLUSH 0
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/* SUNXI_ADC_FIFOS:0x38 */
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#define RXA 23
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#define ADC_RXA_CNT 8
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#define ADC_RXA_INT 3
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#define ADC_RXO_INT 1
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/* SUNXI_ADC_DG:0x4C */
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#define AD_SWP 24
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/* SUNXI_DAC_DAP_CTL:0xf0 */
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#define DDAP_EN 31
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#define DDAP_DRC_EN 29
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#define DDAP_HPF_EN 28
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/* SUNXI_ADC_DAP_CTL:0xf8 */
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#define ADC_DAP0_EN 31
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#define ADC_DRC0_EN 29
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#define ADC_HPF0_EN 28
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/* SUNXI_DAC_DRC_HHPFC : 0x100*/
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#define DAC_HHPF_CONF 0
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/* SUNXI_DAC_DRC_LHPFC : 0x104*/
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#define DAC_LHPF_CONF 0
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/* SUNXI_DAC_DRC_CTRL : 0x108*/
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#define DAC_DRC_DELAY_OUT_STATE 15
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#define DAC_DRC_SIGNAL_DELAY 8
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#define DAC_DRC_DELAY_BUF_EN 7
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#define DAC_DRC_GAIN_MAX_EN 6
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#define DAC_DRC_GAIN_MIN_EN 5
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#define DAC_DRC_NOISE_DET_EN 4
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#define DAC_DRC_SIGNAL_SEL 3
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#define DAC_DRC_DELAY_EN 2
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#define DAC_DRC_LT_EN 1
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#define DAC_DRC_ET_EN 0
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/* SUNXI_ADC_DRC_HHPFC : 0x200*/
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#define ADC_HHPF_CONF 0
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/* SUNXI_ADC_DRC_LHPFC : 0x204*/
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#define ADC_LHPF_CONF 0
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/* SUNXI_ADC_DRC_CTRL : 0x208*/
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#define ADC_DRC_DELAY_OUT_STATE 15
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#define ADC_DRC_SIGNAL_DELAY 8
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#define ADC_DRC_DELAY_BUF_EN 7
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#define ADC_DRC_GAIN_MAX_EN 6
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#define ADC_DRC_GAIN_MIN_EN 5
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#define ADC_DRC_NOISE_DET_EN 4
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#define ADC_DRC_SIGNAL_SEL 3
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#define ADC_DRC_DELAY_EN 2
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#define ADC_DRC_LT_EN 1
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#define ADC_DRC_ER_EN 0
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/* SUNXI_ADCL_ANA_CTL: SUNXI_PR_CFG + 0x00 */
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#define ADCLEN 31
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#define MIC1AMPEN 30
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#define ADC_DITHER_RESET 29
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#define LINEINLEN 23
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#define LINEINLG 22
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#define IOPLINE 20
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#define PGA_CTRL_RCM 18
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#define PGA_IN_VCM_CTRL 16
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#define PGA_GAIN_CTRL 8
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#define ADCL_IOPAAFL 6
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#define ADCLIOPSDML1 4
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#define ADCLIOPSDML2 2
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#define PGA_IOPMICL 0
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/* SUNXI_DAC_ANA_CTL: SUNXI_PR_CFG + 0x10 */
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#define CURRENT_TEST_SELECT 23
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#define VRA2_IOPVRS 20
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#define ILINEOUTAMPS 18
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#define IOPDACS 16
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#define DACLEN 15
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#define LINEOUTL_EN 13
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#define DACLMUTE 12
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#define LINEOUTLDIFFEN 6
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#define LINEOUT_VOL 0
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/* SUNXI_MICBIAS_ANA_CTL: SUNXI_PR_CFG + 0x18 */
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#define MMICBIASEN 7
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#define MBIASSEL 5
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#define MMICBIAS_CHOP_EN 4
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#define MMICBIAS_CHOP_CLK_SEL 2
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/* SUNXI_BIAS_ANA_CTL: SUNXI_PR_CFG + 0x20 */
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#define AC_BIASDATA 0
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#define CODEC_REG_LABEL(constant) {#constant, constant, 0}
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#define CODEC_REG_LABEL_END {NULL, 0, 0}
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/* SUNXI_CODEC_DAP_ENABLE: Whether to use the adc/dac drc/hpf function */
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#define SUNXI_CODEC_DAP_ENABLE
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/* SUNXI_ADC_DAUDIO_SYNC: Whether to enable ADC AEC Drive adaptation */
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/* #define SUNXI_ADC_DAUDIO_SYNC */
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extern int sunxi_codec_get_pcm_trigger_substream_mode(void);
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extern void sunxi_codec_set_pcm_trigger_substream_mode(int value);
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extern int sunxi_codec_get_pcm_adc_sync_flag(void);
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extern void sunxi_codec_set_pcm_adc_sync_flag(int value);
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extern void sunxi_cpudai_adc_drq_enable(bool enable);
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#endif /* __SUN8IW19_CODEC_H */
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