209 lines
6.3 KiB
C
209 lines
6.3 KiB
C
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/*
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* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-10-23 yuzrain the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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#include "md_gpio.h"
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/* PWM device control struct */
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struct pwm_dev_ctrl {
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AD16C4T_TypeDef *timx;
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rt_uint8_t chnm; /* Cannel number */
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struct rt_pwm_configuration *cfg;
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};
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#ifdef BSP_USING_PWM_GP16C2T1
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/* Remember channel configuration */
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static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t1[2] = {
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[0] = {
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.channel = 1,
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.period = 0,
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.pulse = 0
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},
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[1] = {
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.channel = 2,
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.period = 0,
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.pulse = 0
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}
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};
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/* Define static device */
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static struct rt_device_pwm pwm_dev_gp16c2t1;
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static struct pwm_dev_ctrl pwm_dev_gp16c2t1_ctrl;
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#endif
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#ifdef BSP_USING_PWM_GP16C2T4
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/* Remember channel configuration */
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static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t4[2] = {
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[0] = {
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.channel = 1,
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.period = 0,
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.pulse = 0
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},
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[1] = {
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.channel = 2,
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.period = 0,
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.pulse = 0
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}
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};
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/* Define static device */
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static struct rt_device_pwm pwm_dev_gp16c2t4;
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static struct pwm_dev_ctrl pwm_dev_gp16c2t4_ctrl;
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#endif
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static void pwm_auto_config_freq(AD16C4T_TypeDef *timerx, uint32_t ns)
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{
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uint32_t temp_ar;
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uint32_t temp_pres = timerx->PRES & 0xFFFF;
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uint32_t err_cnt = 0;
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/* Automatic setting frequency division ratio */
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while (err_cnt++ < 65536)
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{
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temp_ar = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1);
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if (temp_ar <= 0xFFFF)
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break;
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temp_pres++;
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}
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/* Write back to PRES */
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timerx->PRES = (uint16_t)(temp_pres & 0xFFFF);
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timerx->AR = temp_ar;
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}
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static void pwm_set_duty(AD16C4T_TypeDef *timerx, uint8_t ch, uint32_t ns)
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{
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uint32_t temp_pres = timerx->PRES & 0xFFFF;
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uint64_t tmp = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1);
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if (ch == 1)
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WRITE_REG(timerx->CCVAL1, (uint32_t)tmp);
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else if (ch == 2)
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WRITE_REG(timerx->CCVAL2, (uint32_t)tmp);
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}
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static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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rt_err_t ret = RT_EOK;
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struct pwm_dev_ctrl *dev_ctrl
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= (struct pwm_dev_ctrl *)device->parent.user_data;
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struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
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AD16C4T_TypeDef *timerx = (AD16C4T_TypeDef *)dev_ctrl->timx;
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switch (cmd)
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{
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case PWM_CMD_ENABLE:
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{
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if (cfg->channel == 1)
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SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK);
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else if (cfg->channel == 2)
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SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK);
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break;
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}
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case PWM_CMD_DISABLE:
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{
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if (cfg->channel == 1)
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CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK);
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else if (cfg->channel == 2)
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CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK);
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break;
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}
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case PWM_CMD_SET:
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{
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/* count registers max 0xFFFF, auto adjust prescaler */
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pwm_auto_config_freq(timerx, cfg->period);
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pwm_set_duty(timerx, cfg->channel, cfg->pulse);
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/* Remember configuration */
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dev_ctrl->cfg[cfg->channel-1].period = cfg->period;
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dev_ctrl->cfg[cfg->channel-1].pulse = cfg->pulse;
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break;
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}
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case PWM_CMD_GET:
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{
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cfg->period = dev_ctrl->cfg[cfg->channel-1].period;
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cfg->pulse = dev_ctrl->cfg[cfg->channel-1].pulse;
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break;
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}
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default:
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break;
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}
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return ret;
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}
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const static struct rt_pwm_ops es32f0_pwm_ops =
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{
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es32f0_pwm_control
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};
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int rt_hw_pwm_init(void)
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{
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rt_err_t ret = RT_EOK;
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#ifdef BSP_USING_PWM_GP16C2T1 /* 2 channels */
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/* Open clock */
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SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK);
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/* GPIO configuration */
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md_gpio_set_mode (GPIOB, MD_GPIO_PIN_1, MD_GPIO_MODE_FUNCTION);
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md_gpio_set_mode (GPIOB, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION);
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md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_1, MD_GPIO_AF5);
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md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_2, MD_GPIO_AF5);
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/* Timer configuration */
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MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK,
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(6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS));
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MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK,
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(6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS));
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SET_BIT(GP16C2T1->BDCFG, AD16C4T_BDCFG_GOEN_MSK);
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SET_BIT(GP16C2T1->CON1, AD16C4T_CON1_CNTEN_MSK);
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pwm_dev_gp16c2t1_ctrl.chnm = 2;
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pwm_dev_gp16c2t1_ctrl.timx = GP16C2T1;
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pwm_dev_gp16c2t1_ctrl.cfg = pwm_ch_cfg_gp16c2t1;
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/* Register PWM device */
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ret = rt_device_pwm_register(&pwm_dev_gp16c2t1,
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"pwm1", &es32f0_pwm_ops, &pwm_dev_gp16c2t1_ctrl);
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#endif
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#ifdef BSP_USING_PWM_GP16C2T4 /* 2 channels */
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/* Open clock */
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SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK);
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/* GPIO configuration */
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md_gpio_set_mode (GPIOB, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION);
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md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION);
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md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_12, MD_GPIO_AF5);
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md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF5);
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/* Timer configuration */
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MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK,
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(6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS));
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MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK,
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(6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS));
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SET_BIT(GP16C2T4->BDCFG, AD16C4T_BDCFG_GOEN_MSK);
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SET_BIT(GP16C2T4->CON1, AD16C4T_CON1_CNTEN_MSK);
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pwm_dev_gp16c2t4_ctrl.chnm = 2;
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pwm_dev_gp16c2t4_ctrl.timx = GP16C2T4;
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pwm_dev_gp16c2t4_ctrl.cfg = pwm_ch_cfg_gp16c2t4;
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/* Register PWM device */
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ret = rt_device_pwm_register(&pwm_dev_gp16c2t4,
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"pwm2", &es32f0_pwm_ops, &pwm_dev_gp16c2t4_ctrl);
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#endif
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return ret;
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}
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INIT_DEVICE_EXPORT(rt_hw_pwm_init);
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