2019-01-28 19:24:33 +08:00
|
|
|
/*
|
2021-03-14 15:33:55 +08:00
|
|
|
* Copyright (c) 2006-2021, RT-Thread Development Team
|
2019-01-28 19:24:33 +08:00
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*
|
|
|
|
* Change Logs:
|
|
|
|
* Date Author Notes
|
|
|
|
* 2018-11-5 SummerGift change to new framework
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __BOARD_H__
|
|
|
|
#define __BOARD_H__
|
|
|
|
|
|
|
|
#include <stm32l4xx.h>
|
2023-12-04 00:11:29 +08:00
|
|
|
#include <rtconfig.h>
|
2019-01-28 19:24:33 +08:00
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
extern "C" {
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
|
|
|
|
#define STM32_FLASH_SIZE (1024 * 1024)
|
|
|
|
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
|
|
|
|
|
|
|
|
#define STM32_SRAM1_SIZE (96)
|
|
|
|
#define STM32_SRAM1_START (0x20000000)
|
|
|
|
#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024)
|
|
|
|
|
|
|
|
#define HEAP_BEGIN STM32_SRAM1_START
|
|
|
|
#define HEAP_END STM32_SRAM1_END
|
|
|
|
|
|
|
|
void SystemClock_Config(void);
|
|
|
|
|
2019-05-06 18:30:24 +08:00
|
|
|
#ifdef RT_USING_PM
|
|
|
|
|
|
|
|
void SystemClock_MSI_ON(void);
|
|
|
|
void SystemClock_MSI_OFF(void);
|
|
|
|
void SystemClock_80M(void);
|
|
|
|
void SystemClock_24M(void);
|
|
|
|
void SystemClock_2M(void);
|
|
|
|
void SystemClock_ReConfig(uint8_t mode);
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2019-01-28 19:24:33 +08:00
|
|
|
#ifdef __cplusplus
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|