2021-10-27 18:51:05 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2021-11-04 20:31:55 +08:00
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* 2021-11-30 flybreak first version
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2021-10-27 18:51:05 +08:00
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*/
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include "board.h"
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#include "hal_data.h"
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2022-07-07 17:12:56 +08:00
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#include "drv_common.h"
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2021-10-27 18:51:05 +08:00
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2022-03-15 09:48:05 +08:00
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#if defined(RT_USING_FAL)
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2021-10-27 18:51:05 +08:00
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#include "fal.h"
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#endif
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//#define DRV_DEBUG
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#define LOG_TAG "drv.flash"
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#ifdef DRV_DEBUG
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#define DBG_LVL DBG_LOG
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#else
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#define DBG_LVL DBG_INFO
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#endif /* DRV_DEBUG */
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#include <rtdbg.h>
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2022-07-07 17:12:56 +08:00
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#if BSP_FEATURE_FLASH_HP_VERSION
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/* FLASH API */
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#define R_FLASH_Open R_FLASH_HP_Open
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#define R_FLASH_Reset R_FLASH_HP_Reset
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#define R_FLASH_Write R_FLASH_HP_Write
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#define R_FLASH_Erase R_FLASH_HP_Erase
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#define R_FLASH_StartUpAreaSelect R_FLASH_HP_StartUpAreaSelect
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/* BSP_FEATURE_FLASH */
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#define FLASH_CF_WRITE_SIZE BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE
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#else /* FLASH LP */
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/* FLASH API */
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#define R_FLASH_Open R_FLASH_LP_Open
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#define R_FLASH_Reset R_FLASH_LP_Reset
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#define R_FLASH_Write R_FLASH_LP_Write
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#define R_FLASH_Erase R_FLASH_LP_Erase
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#define R_FLASH_StartUpAreaSelect R_FLASH_LP_StartUpAreaSelect
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/* BSP_FEATURE_FLASH */
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#define FLASH_CF_WRITE_SIZE BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE
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#endif
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2021-10-27 18:51:05 +08:00
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int _flash_init(void)
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{
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fsp_err_t err = FSP_SUCCESS;
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/* Open Flash_HP */
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2022-07-07 17:12:56 +08:00
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err = R_FLASH_Open(&g_flash_ctrl, &g_flash_cfg);
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2021-10-27 18:51:05 +08:00
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/* Handle Error */
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if (FSP_SUCCESS != err)
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{
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LOG_E("\r\n Flah_HP_Open API failed");
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}
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/* Setup Default Block 0 as Startup Setup Block */
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2022-07-07 17:12:56 +08:00
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err = R_FLASH_StartUpAreaSelect(&g_flash_ctrl, FLASH_STARTUP_AREA_BLOCK0, true);
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2021-10-27 18:51:05 +08:00
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if (err != FSP_SUCCESS)
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{
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LOG_E("\r\n Flah_HP_StartUpAreaSelect API failed");
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}
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return 0;
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}
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/**
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* Read data from flash.
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* @note This operation's units is word.
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*
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* @param addr flash address
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* @param buf buffer to store read data
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* @param size read bytes size
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*
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* @return result
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*/
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int _flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
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{
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size_t i;
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for (i = 0; i < size; i++, buf++, addr++)
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{
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*buf = *(rt_uint8_t *) addr;
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}
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return size;
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}
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/**
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* Write data to flash.
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* @note This operation's units is word.
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* @note This operation must after erase. @see flash_erase.
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*
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* @param addr flash address
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* @param buf the write data buffer
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* @param size write bytes size
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*
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* @return result
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*/
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int _flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
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{
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rt_err_t result = RT_EOK;
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rt_base_t level;
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fsp_err_t err = FSP_SUCCESS;
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size_t written_size = 0;
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2022-07-07 17:12:56 +08:00
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if (size % FLASH_CF_WRITE_SIZE)
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2021-10-27 18:51:05 +08:00
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{
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2022-07-07 17:12:56 +08:00
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LOG_E("Flash Write size must be an integer multiple of %d", FLASH_CF_WRITE_SIZE);
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2021-10-27 18:51:05 +08:00
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}
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while (written_size < size)
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{
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level = rt_hw_interrupt_disable();
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2022-07-07 17:12:56 +08:00
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R_FLASH_Reset(&g_flash_ctrl);
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2021-10-27 18:51:05 +08:00
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/* Write code flash data*/
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2022-07-07 17:12:56 +08:00
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err = R_FLASH_Write(&g_flash_ctrl, (uint32_t)(buf + written_size), addr + written_size, FLASH_CF_WRITE_SIZE);
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2021-10-27 18:51:05 +08:00
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rt_hw_interrupt_enable(level);
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/* Error Handle */
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if (FSP_SUCCESS != err)
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{
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LOG_E("Write API failed");
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return -RT_EIO;
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}
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2022-07-07 17:12:56 +08:00
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written_size += FLASH_CF_WRITE_SIZE;
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2021-10-27 18:51:05 +08:00
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}
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if (result != RT_EOK)
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{
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return result;
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}
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return size;
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}
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2023-11-16 16:51:32 +08:00
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typedef bool (*block_func)(int no, size_t addr, size_t size, void *parm1, void *parm2, void *parm3);
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void fal_block_iter(const struct fal_flash_dev *flash, block_func func, void *parm1, void *parm2, void *parm3)
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{
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int no = 0;
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size_t addr = flash->addr;
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for (int i = 0; i < FAL_DEV_BLK_MAX; i++)
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{
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/* blocks[i] */
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const struct flash_blk *cur_blk = &flash->blocks[i];
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if (cur_blk->size == 0 || cur_blk->count == 0)
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{
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break;
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}
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int j = cur_blk->count;
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while (j--)
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{
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/* block_no */
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if (func(no, addr, cur_blk->size, parm1, parm2, parm3) == true)
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{
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return;
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}
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addr += cur_blk->size;
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no ++;
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}
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}
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}
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bool calculate_block_num(int no, size_t addr, size_t size, void *erase_addr, void *erase_size, void *number)
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{
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rt_uint32_t e_addr = (rt_uint32_t)erase_addr;
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size_t e_size = (size_t)erase_size;
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int *i = (int *)number;
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LOG_D("block_num: no: %d, addr is (0x%p), size: %d\n, i:%d", no, addr, size, *i);
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LOG_D("erase_addr: (0x%p), erase_size: %d\n", e_addr, e_size);
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if (e_addr >= addr && e_addr < addr + size)
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{
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(*i) ++;
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return false;
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}
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else if (addr > e_addr && addr < e_addr + e_size)
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{
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(*i) ++;
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return false;
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}
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else if (addr >= e_addr + e_size)
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{
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return true;
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}
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return false;
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}
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2021-10-27 18:51:05 +08:00
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/**
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* Erase data on flash.
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* @note This operation is irreversible.
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* @note This operation's units is different which on many chips.
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*
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* @param addr flash address
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* @param size erase bytes size
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*
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* @return result
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*/
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2022-07-07 17:12:56 +08:00
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#if BSP_FEATURE_FLASH_HP_VERSION
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int _flash_hp0_erase(rt_uint32_t addr, size_t size)
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#else
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int _flash_lp_erase(rt_uint32_t addr, size_t size)
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#endif
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2021-10-27 18:51:05 +08:00
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{
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fsp_err_t err = FSP_SUCCESS;
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rt_base_t level;
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2023-11-16 16:51:32 +08:00
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int block_num = 0;
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2021-10-27 18:51:05 +08:00
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2023-11-16 16:51:32 +08:00
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if ((addr + size) > BSP_FEATURE_FLASH_CODE_FLASH_START + BSP_ROM_SIZE_BYTES)
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2021-10-27 18:51:05 +08:00
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{
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LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
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return -RT_EINVAL;
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}
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if (size < 1)
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{
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return -RT_EINVAL;
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}
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level = rt_hw_interrupt_disable();
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2022-07-07 17:12:56 +08:00
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R_FLASH_Reset(&g_flash_ctrl);
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2023-11-16 16:51:32 +08:00
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fal_block_iter(&_onchip_flash_hp0, &calculate_block_num, (void *)addr, (void *)size, &block_num);
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2021-10-27 18:51:05 +08:00
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/* Erase Block */
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2022-07-07 17:12:56 +08:00
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#if BSP_FEATURE_FLASH_HP_VERSION
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err = R_FLASH_Erase(&g_flash_ctrl,
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RT_ALIGN_DOWN(addr, BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE),
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2023-11-16 16:51:32 +08:00
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block_num);
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2022-07-07 17:12:56 +08:00
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#else
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err = R_FLASH_Erase(&g_flash_ctrl,
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RT_ALIGN_DOWN(addr, BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE),
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((size - 1) / BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE + 1));
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#endif
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2021-10-27 18:51:05 +08:00
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rt_hw_interrupt_enable(level);
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if (err != FSP_SUCCESS)
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{
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2022-07-07 17:12:56 +08:00
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LOG_E("Erase failed:addr (0x%p), size %d", (void *)addr, size);
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2021-10-27 18:51:05 +08:00
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return -RT_EIO;
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}
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LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
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return size;
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}
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2022-03-15 09:48:05 +08:00
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#if defined(RT_USING_FAL)
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2021-10-27 18:51:05 +08:00
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2022-07-07 17:12:56 +08:00
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#if BSP_FEATURE_FLASH_HP_VERSION
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2021-10-27 18:51:05 +08:00
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2022-07-07 17:12:56 +08:00
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static int fal_flash_hp0_read(long offset, rt_uint8_t *buf, size_t size);
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static int fal_flash_hp0_write(long offset, const rt_uint8_t *buf, size_t size);
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static int fal_flash_hp0_erase(long offset, size_t size);
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2021-10-27 18:51:05 +08:00
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2022-07-07 17:12:56 +08:00
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const struct fal_flash_dev _onchip_flash_hp0 =
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{
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"onchip_flash_hp0",
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2023-11-16 16:51:32 +08:00
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BSP_FEATURE_FLASH_CODE_FLASH_START,
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BSP_ROM_SIZE_BYTES,
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2022-07-07 17:12:56 +08:00
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BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE,
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{
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_flash_init,
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fal_flash_hp0_read,
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fal_flash_hp0_write,
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fal_flash_hp0_erase
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},
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(BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE * 8)
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2023-11-16 16:51:32 +08:00
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, {
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{
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.size = BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE,
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.count = BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE / BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE
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},
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{
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.size = BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE,
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.count = (BSP_ROM_SIZE_BYTES - BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE) / BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE
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},
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}
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2022-07-07 17:12:56 +08:00
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};
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/* code flash region0 */
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static int fal_flash_hp0_read(long offset, rt_uint8_t *buf, size_t size)
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{
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return _flash_read(_onchip_flash_hp0.addr + offset, buf, size);
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}
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2021-10-27 18:51:05 +08:00
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2022-07-07 17:12:56 +08:00
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static int fal_flash_hp0_write(long offset, const rt_uint8_t *buf, size_t size)
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{
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return _flash_write(_onchip_flash_hp0.addr + offset, buf, size);
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}
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2021-10-27 18:51:05 +08:00
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2022-07-07 17:12:56 +08:00
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static int fal_flash_hp0_erase(long offset, size_t size)
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{
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return _flash_hp0_erase(_onchip_flash_hp0.addr + offset, size);
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}
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2021-10-27 18:51:05 +08:00
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2022-07-07 17:12:56 +08:00
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#else /* flash lp code flash */
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static int fal_flash_lp_read(long offset, rt_uint8_t *buf, size_t size);
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static int fal_flash_lp_write(long offset, const rt_uint8_t *buf, size_t size);
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static int fal_flash_lp_erase(long offset, size_t size);
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const struct fal_flash_dev _onchip_flash_lp =
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{
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"onchip_flash_lp",
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FLASH_START_ADDRESS,
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BSP_ROM_SIZE_BYTES,
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BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE,
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{
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_flash_init,
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fal_flash_lp_read,
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fal_flash_lp_write,
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fal_flash_lp_erase
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},
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(BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE * 8)
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};
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static int fal_flash_lp_read(long offset, rt_uint8_t *buf, size_t size)
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2021-10-27 18:51:05 +08:00
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{
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2022-07-07 17:12:56 +08:00
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return _flash_read(_onchip_flash_lp.addr + offset, buf, size);
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2021-10-27 18:51:05 +08:00
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}
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2022-07-07 17:12:56 +08:00
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static int fal_flash_lp_write(long offset, const rt_uint8_t *buf, size_t size)
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2021-10-27 18:51:05 +08:00
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{
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2022-07-07 17:12:56 +08:00
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return _flash_write(_onchip_flash_lp.addr + offset, buf, size);
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2021-10-27 18:51:05 +08:00
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}
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2022-07-07 17:12:56 +08:00
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static int fal_flash_lp_erase(long offset, size_t size)
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2021-10-27 18:51:05 +08:00
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{
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2022-07-07 17:12:56 +08:00
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return _flash_lp_erase(_onchip_flash_lp.addr + offset, size);
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2021-10-27 18:51:05 +08:00
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}
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2022-07-07 17:12:56 +08:00
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#endif
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2021-10-27 18:51:05 +08:00
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#endif
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