184 lines
4.6 KiB
C
184 lines
4.6 KiB
C
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/**
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**************************************************************************
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* @file at32f415_wdt.h
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* @version v2.0.4
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* @date 2022-04-02
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* @brief at32f415 wdt header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32F415_WDT_H
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#define __AT32F415_WDT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32f415.h"
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/** @addtogroup AT32F415_periph_driver
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* @{
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*/
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/** @addtogroup WDT
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* @{
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*/
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/** @defgroup WDT_flags_definition
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* @brief wdt flag
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* @{
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*/
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#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
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#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
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/**
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* @}
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*/
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/** @defgroup WDT_exported_types
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* @{
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*/
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/**
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* @brief wdt division value type
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*/
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typedef enum
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{
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WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
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WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
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WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
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WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
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WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
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WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
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WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
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} wdt_division_type;
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/**
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* @brief wdt cmd value type
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*/
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typedef enum
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{
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WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
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WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
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WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
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WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
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} wdt_cmd_value_type;
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/**
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* @brief type define wdt register all
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*/
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typedef struct
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{
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/**
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* @brief wdt cmd register, offset:0x00
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*/
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union
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{
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__IO uint32_t cmd;
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struct
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{
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__IO uint32_t cmd : 16;/* [15:0] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} cmd_bit;
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};
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/**
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* @brief wdt div register, offset:0x04
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*/
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union
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{
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__IO uint32_t div;
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struct
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{
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__IO uint32_t div : 3; /* [2:0] */
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__IO uint32_t reserved1 : 29;/* [31:3] */
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} div_bit;
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};
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/**
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* @brief wdt rld register, offset:0x08
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*/
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union
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{
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__IO uint32_t rld;
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struct
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{
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__IO uint32_t rld : 12;/* [11:0] */
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__IO uint32_t reserved1 : 20;/* [31:12] */
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} rld_bit;
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};
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/**
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* @brief wdt sts register, offset:0x0C
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*/
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union
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{
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__IO uint32_t sts;
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struct
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{
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__IO uint32_t divf : 1; /* [0] */
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__IO uint32_t rldf : 1; /* [1] */
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__IO uint32_t reserved1 : 30;/* [31:2] */
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} sts_bit;
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};
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} wdt_type;
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/**
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* @}
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*/
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#define WDT ((wdt_type *) WDT_BASE)
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/** @defgroup WDT_exported_functions
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* @{
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*/
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void wdt_enable(void);
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void wdt_counter_reload(void);
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void wdt_reload_value_set(uint16_t reload_value);
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void wdt_divider_set(wdt_division_type division);
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void wdt_register_write_enable( confirm_state new_state);
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flag_status wdt_flag_get(uint16_t wdt_flag);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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