2021-05-21 18:43:59 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-04-11 Carl the first version
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*/
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#include "drv_qspi.h"
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#include <rtthread.h>
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#include "rtdevice.h"
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#include "ft_qspi.h"
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#include "ft_parameters.h"
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#ifdef BSP_USE_QSPI
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#define DRV_DEBUG
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#define LOG_TAG "drv.qspi"
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#include <drv_log.h>
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struct ft2004_qspi_bus
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{
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FQSpi_t fqspi;
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char *name;
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rt_uint32_t init; /* 1 is init already */
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};
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static struct rt_spi_bus _qspi_bus;
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static struct ft2004_qspi_bus _ft2004_qspi_bus;
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static int ft2004_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configuration *qspi_cfg)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(qspi_cfg != RT_NULL);
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// struct rt_spi_configuration *cfg = &qspi_cfg->parent;
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struct ft2004_qspi_bus *qspi_bus_p = device->parent.bus->parent.user_data;
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if (qspi_bus_p->init == 0)
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{
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qspi_bus_p->init = 1;
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FQSpi_CfgInitialize(&qspi_bus_p->fqspi, FQSpi_LookupConfig(0));
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}
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return RT_EOK;
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}
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static rt_err_t ft2004_cmdOperation(struct ft2004_qspi_bus *qspi_bus_p, struct rt_spi_message *message)
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{
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struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
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const rt_uint8_t *sndb = message->send_buf;
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rt_uint8_t *rcvb = message->recv_buf;
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ft_error_t ret;
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RT_ASSERT(qspi_bus_p != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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struct FQSpi_CmdPack cmd_pack = {0};
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if (qspi_message->instruction.qspi_lines == 0)
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{
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LOG_E("instruction is not valid");
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2023-03-17 12:12:16 +08:00
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return -RT_ERROR;
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2021-05-21 18:43:59 +08:00
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}
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cmd_pack.cmd = qspi_message->instruction.content;
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if (qspi_message->address.qspi_lines != 0)
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{
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cmd_pack.flags |= FQSPI_CMD_NEED_ADDR_MASK;
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cmd_pack.addr = qspi_message->address.content;
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}
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if (qspi_message->address.size == 24)
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{
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cmd_pack.flags |= FQSPI_CMD_ADDRESS_3BYTE_MASK;
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}
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else if (qspi_message->address.size == 32)
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{
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cmd_pack.flags |= FQSPI_CMD_ADDRESS_4BYTE_MASK;
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}
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if (qspi_message->qspi_data_lines != 0)
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{
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if (sndb && (message->length > 0))
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{
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cmd_pack.flags |= FQSPI_CMD_NEED_SET_MASK;
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cmd_pack.txBuf = sndb;
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cmd_pack.length = message->length;
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}
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else if (rcvb && (message->length > 0))
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{
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cmd_pack.flags |= FQSPI_CMD_NEED_GET_MASK;
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cmd_pack.rxBuf = rcvb;
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cmd_pack.length = message->length;
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}
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else
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{
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cmd_pack.flags &= ~(FQSPI_CMD_NEED_GET_MASK | FQSPI_CMD_NEED_SET_MASK);
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}
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}
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if (qspi_message->dummy_cycles)
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{
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cmd_pack.flags |= FQSPI_CMD_NEED_DUMMY_MASK;
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cmd_pack.dummyCycle = qspi_message->dummy_cycles;
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}
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if (cmd_pack.cmd == 0x20)
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{
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if (qspi_message->address.size == 32)
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{
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cmd_pack.cmd = 0xdc;
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}
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}
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#ifdef BSP_QSPI_DEBUG
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LOG_I("flags %x", cmd_pack.flags);
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#endif
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ret = FQSpi_CmdOperation(&qspi_bus_p->fqspi, &cmd_pack);
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#ifdef BSP_QSPI_DEBUG
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if (ret == FQSPI_SUCCESS)
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if (cmd_pack.cmd == 5)
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{
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LOG_I("cmd05 0x%x", cmd_pack.rxBuf[0]);
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}
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#endif
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2023-03-17 12:12:16 +08:00
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return (ret == FQSPI_SUCCESS) ? RT_EOK : -RT_ERROR;
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2021-05-21 18:43:59 +08:00
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}
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2023-03-17 12:12:16 +08:00
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static rt_ssize_t ft2004_qspi_xfer(struct ft2004_qspi_bus *qspi_bus_p, struct rt_spi_message *message)
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2021-05-21 18:43:59 +08:00
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{
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struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
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2023-03-17 12:12:16 +08:00
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rt_ssize_t ret_length = 0;
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2021-05-21 18:43:59 +08:00
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const rt_uint8_t *sndb = message->send_buf;
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rt_uint8_t *rcvb = message->recv_buf;
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rt_int32_t length = message->length;
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rt_uint32_t cmd;
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rt_uint32_t addr;
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FQSpi_t *qspi_p;
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FQSpi_Config_t *qspi_config_p;
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struct FQSpi_DataPack data_pack = {0};
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qspi_p = &qspi_bus_p->fqspi;
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qspi_config_p = &qspi_bus_p->fqspi.config;
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cmd = qspi_message->instruction.content;
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addr = qspi_message->address.content;
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#ifdef BSP_QSPI_DEBUG
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LOG_I("cmd is %x ", cmd);
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LOG_I("length %d , rcvb %x sndb %x addr %x dummy_cycles %x ", length, rcvb, sndb, addr, qspi_message->dummy_cycles);
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#endif
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if (qspi_config_p->channel >= FT_QSPI_MAX_CS_NUM)
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{
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LOG_E("invalid channel[%x] ", qspi_config_p->channel);
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2023-03-17 12:12:16 +08:00
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return -RT_ERROR;
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2021-05-21 18:43:59 +08:00
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}
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switch (cmd)
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{
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case FQSPI_FLASH_CMD_PP:
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{
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if (RT_NULL != sndb)
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{
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data_pack.cmd = cmd;
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data_pack.addr = addr;
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if (qspi_message->address.size == 24)
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{
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data_pack.flags |= FQSPI_DATA_ADDRESS_3BYTE_MASK;
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}
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else
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{
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data_pack.flags |= FQSPI_DATA_ADDRESS_4BYTE_MASK;
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}
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LOG_E("write flags %x ", data_pack.flags);
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data_pack.txBuf = sndb;
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data_pack.length = length;
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ret_length = ((FQSpi_Write(qspi_p, &data_pack) == FQSPI_SUCCESS) ? length : 0);
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}
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else
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{
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LOG_E("pp cmd %x sndb is null", cmd);
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ret_length = 0;
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}
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}
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break;
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case FQSPI_FLASH_CMD_WRDI: /* for sufd qspi fast read */
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FQSpi_FlashRegSet(qspi_p, cmd, RT_NULL, 0);
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case FQSPI_FLASH_CMD_READ:
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{
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if (RT_NULL != rcvb)
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{
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data_pack.cmd = FQSPI_FLASH_CMD_READ;
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data_pack.addr = addr;
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if (qspi_message->address.size == 24)
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{
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data_pack.flags |= FQSPI_DATA_ADDRESS_3BYTE_MASK;
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}
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else
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{
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data_pack.flags |= FQSPI_DATA_ADDRESS_4BYTE_MASK;
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}
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if (qspi_message->dummy_cycles)
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{
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data_pack.flags |= FQSPI_DATA_NEED_DUMMY_MASK;
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data_pack.dummyCycle = qspi_message->dummy_cycles;
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}
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data_pack.rxBuf = rcvb;
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data_pack.length = length;
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ret_length = ((FQSpi_Read(qspi_p, &data_pack) == FQSPI_SUCCESS) ? length : 0);
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}
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else
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{
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// LOG_E("read cmd %x rcvb is null", cmd);
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ret_length = 0;
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}
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}
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break;
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default:
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{
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if (ft2004_cmdOperation(qspi_bus_p, message) == RT_EOK)
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{
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ret_length = 1;
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}
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else
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{
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LOG_E("ft2004_cmdOperation error");
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ret_length = 0;
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}
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}
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}
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return ret_length;
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}
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static rt_uint32_t qspixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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struct ft2004_qspi_bus *qspi_bus_p = device->bus->parent.user_data;
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return ft2004_qspi_xfer(qspi_bus_p, message);
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}
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static rt_err_t qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device;
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return ft2004_qspi_init(qspi_device, &qspi_device->config);
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}
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static const struct rt_spi_ops ft2004_qspi_ops =
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{
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.configure = qspi_configure,
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.xfer = qspixfer,
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};
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static int ft2004_qspi_register_bus(struct ft2004_qspi_bus *qspi_bus, const char *name)
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{
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RT_ASSERT(qspi_bus != RT_NULL);
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RT_ASSERT(name != RT_NULL);
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_qspi_bus.parent.user_data = qspi_bus;
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return rt_qspi_bus_register(&_qspi_bus, name, &ft2004_qspi_ops);
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}
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rt_err_t ft2004_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
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{
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struct rt_qspi_device *qspi_device = RT_NULL;
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rt_err_t result = RT_EOK;
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RT_ASSERT(bus_name != RT_NULL);
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RT_ASSERT(device_name != RT_NULL);
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RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
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qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
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if (qspi_device == RT_NULL)
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{
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LOG_E("no memory, qspi bus attach device failed!");
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2023-03-23 12:56:38 +08:00
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result = -RT_ENOMEM;
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2021-05-21 18:43:59 +08:00
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goto __exit;
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}
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qspi_device->enter_qspi_mode = enter_qspi_mode;
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qspi_device->exit_qspi_mode = exit_qspi_mode;
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qspi_device->config.qspi_dl_width = data_line_width;
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result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, RT_NULL);
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__exit:
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if (result != RT_EOK)
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{
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if (qspi_device)
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{
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rt_free(qspi_device);
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}
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}
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return result;
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}
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static int rt_hw_qspi_bus_init(void)
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{
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return ft2004_qspi_register_bus(&_ft2004_qspi_bus, FT2004_QSPI_NAME);
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}
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INIT_BOARD_EXPORT(rt_hw_qspi_bus_init);
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#ifdef BSP_QSPI_DEBUG
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static void cmd05_check(void)
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{
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struct FQSpi_CmdPack cmd_pack = {0};
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u8 rx_buffer[1];
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cmd_pack.cmd = 0x6;
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FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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rt_memset(&cmd_pack, 0, sizeof(&cmd_pack));
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cmd_pack.cmd = 0x5;
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cmd_pack.flags = FQSPI_CMD_NEED_GET_MASK;
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cmd_pack.rxBuf = rx_buffer;
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cmd_pack.length = sizeof(rx_buffer);
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FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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for (u32 i = 0; i < cmd_pack.length; i++)
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{
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LOG_I("cnt %d, 0x%x ", i, rx_buffer[i]);
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}
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rt_memset(&cmd_pack, 0, sizeof(&cmd_pack));
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cmd_pack.cmd = 0x4;
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FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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rt_memset(&cmd_pack, 0, sizeof(&cmd_pack));
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cmd_pack.cmd = 0x5;
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cmd_pack.flags = FQSPI_CMD_NEED_GET_MASK;
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cmd_pack.rxBuf = rx_buffer;
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cmd_pack.length = sizeof(rx_buffer);
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FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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for (u32 i = 0; i < cmd_pack.length; i++)
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{
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LOG_I("cnt %d, 0x%x ", i, rx_buffer[i]);
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}
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}
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MSH_CMD_EXPORT_ALIAS(cmd05_check, cmd05_check, cmd05_check);
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#endif
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#ifdef BSP_QSPI_DEBUG
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static void cmd35_check(void)
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{
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struct FQSpi_CmdPack cmd_pack = {0};
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u8 rx_buffer[1];
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cmd_pack.cmd = 0x6;
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FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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rt_memset(&cmd_pack, 0, sizeof(&cmd_pack));
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cmd_pack.cmd = 0x5;
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cmd_pack.flags = FQSPI_CMD_NEED_GET_MASK;
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cmd_pack.rxBuf = rx_buffer;
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cmd_pack.length = sizeof(rx_buffer);
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FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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for (u32 i = 0; i < cmd_pack.length; i++)
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{
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LOG_I("cnt %d, 0x%x ", i, rx_buffer[i]);
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}
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cmd_pack.cmd = 0xB7;
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FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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rt_memset(&cmd_pack, 0, sizeof(&cmd_pack));
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cmd_pack.cmd = 0x35;
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cmd_pack.flags = FQSPI_CMD_NEED_GET_MASK;
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cmd_pack.rxBuf = rx_buffer;
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cmd_pack.length = sizeof(rx_buffer);
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FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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for (u32 i = 0; i < cmd_pack.length; i++)
|
|
|
|
{
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|
LOG_I("cnt %d, 0x%x ", i, rx_buffer[i]);
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}
|
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|
}
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MSH_CMD_EXPORT_ALIAS(cmd35_check, cmd35_check, cmd35_check);
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|
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|
#endif
|
|
|
|
#ifdef BSP_QSPI_DEBUG
|
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|
|
static void cmd15_check(void)
|
|
|
|
{
|
|
|
|
struct FQSpi_CmdPack cmd_pack = {0};
|
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|
|
u8 rx_buffer[1];
|
|
|
|
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|
|
|
// cmd_pack.cmd = 0xB7;
|
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|
|
// FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
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|
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|
|
rt_memset(&cmd_pack, 0, sizeof(&cmd_pack));
|
|
|
|
cmd_pack.cmd = 0x15;
|
|
|
|
cmd_pack.flags = FQSPI_CMD_NEED_GET_MASK;
|
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|
|
cmd_pack.rxBuf = rx_buffer;
|
|
|
|
cmd_pack.length = sizeof(rx_buffer);
|
|
|
|
|
|
|
|
FQSpi_CmdOperation(&_ft2004_qspi_bus.fqspi, &cmd_pack);
|
|
|
|
|
|
|
|
for (u32 i = 0; i < cmd_pack.length; i++)
|
|
|
|
{
|
|
|
|
LOG_I("cnt %d, 0x%x ", i, rx_buffer[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
MSH_CMD_EXPORT_ALIAS(cmd15_check, cmd15_check, cmd15_check);
|
|
|
|
#endif
|
|
|
|
#endif
|