286 lines
8.9 KiB
C
286 lines
8.9 KiB
C
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/*
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* Copyright (c) 2008-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!
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* @file mmu.c
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* @brief System memory arangement.
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*/
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#include "cortex_a.h"
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#include "mmu.h"
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#include "arm_cp_registers.h"
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////////////////////////////////////////////////////////////////////////////////
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// Definitions
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////////////////////////////////////////////////////////////////////////////////
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//! @brief Size in bytes of the first-level page table.
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#define MMU_L1_PAGE_TABLE_SIZE (16 * 1024)
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//! @brief First-level 1MB section descriptor entry.
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typedef union mmu_l1_section {
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uint32_t u;
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struct {
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uint32_t id:2; //!< ID
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uint32_t b:1; //!< Bufferable
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uint32_t c:1; //!< Cacheable
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uint32_t xn:1; //!< Execute-not
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uint32_t domain:4; //!< Domain
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uint32_t _impl_defined:1; //!< Implementation defined, should be zero.
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uint32_t ap1_0:2; //!< Access permissions AP[1:0]
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uint32_t tex:3; //!< TEX remap
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uint32_t ap2:1; //!< Access permissions AP[2]
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uint32_t s:1; //!< Shareable
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uint32_t ng:1; //!< Not-global
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uint32_t _zero:1; //!< Should be zero.
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uint32_t ns:1; //!< Non-secure
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uint32_t address:12; //!< Physical base address
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};
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} mmu_l1_section_t;
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enum {
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kMMU_L1_Section_ID = 2, //!< ID value for a 1MB section first-level entry.
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kMMU_L1_Section_Address_Shift = 20 //!< Bit offset of the physical base address field.
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};
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////////////////////////////////////////////////////////////////////////////////
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// Externs
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////////////////////////////////////////////////////////////////////////////////
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extern char __l1_page_table_start;
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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void mmu_enable()
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{
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// invalidate all tlb
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arm_unified_tlb_invalidate();
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// read SCTLR
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uint32_t sctlr;
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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// set MMU enable bit
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sctlr |= BM_SCTLR_M;
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// write modified SCTLR
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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}
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void mmu_disable()
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{
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// read current SCTLR
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uint32_t sctlr;
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_ARM_MRC(15, 0, sctlr, 1, 0, 0);
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// clear MMU enable bit
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sctlr &=~ BM_SCTLR_M;
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// write modified SCTLR
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_ARM_MCR(15, 0, sctlr, 1, 0, 0);
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}
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void mmu_init()
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{
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// Get the L1 page table base address.
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uint32_t * table = (uint32_t *)&__l1_page_table_start;
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uint32_t share_attr = kShareable;
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// write table address to TTBR0
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_ARM_MCR(15, 0, table, 2, 0, 0);
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// set Client mode for all Domains
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uint32_t dacr = 0x55555555;
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_ARM_MCR(15, 0, dacr, 3, 0, 0); // MCR p15, 0, <Rd>, c3, c0, 0 ; Write DACR
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// Clear the L1 table.
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bzero(table, MMU_L1_PAGE_TABLE_SIZE);
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// Create default mappings.
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mmu_map_l1_range(0x00000000, 0x00000000, 0x00900000, kStronglyOrdered, kShareable, kRWAccess); // ROM and peripherals
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mmu_map_l1_range(0x00900000, 0x00900000, 0x00100000, kStronglyOrdered, kShareable, kRWAccess); // OCRAM
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mmu_map_l1_range(0x00a00000, 0x00a00000, 0x0f600000, kStronglyOrdered, kShareable, kRWAccess); // More peripherals
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// Check whether SMP is enabled. If it is not, then we don't want to make SDRAM shareable.
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uint32_t actlr = 0x0;
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_ARM_MRC(15, 0, actlr, 1, 0, 1);
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if (actlr & BM_ACTLR_SMP)
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{
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share_attr = kShareable;
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}
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else
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{
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share_attr = kNonshareable;
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}
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#if defined(CHIP_MX6DQ) || defined(CHIP_MX6SDL)
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mmu_map_l1_range(0x10000000, 0x10000000, 0x80000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 2GB DDR
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#elif defined(CHIP_MX6SL) || defined(CHIP_MX6UL)
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mmu_map_l1_range(0x80000000, 0x80000000, 0x40000000, kOuterInner_WB_WA, share_attr, kRWAccess); // 1GB DDR
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#else
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#error Unknown chip type!
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#endif
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}
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void mmu_map_l1_range(uint32_t pa, uint32_t va, uint32_t length, mmu_memory_type_t memoryType, mmu_shareability_t isShareable, mmu_access_t access)
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{
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register mmu_l1_section_t entry;
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entry.u = 0;
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// Set constant attributes.
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entry.id = kMMU_L1_Section_ID;
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entry.xn = 0; // Allow execution
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entry.domain = 0; // Domain 0
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entry.ng = 0; // Global
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entry.ns = 0; // Secure
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// Set attributes based on the selected memory type.
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switch (memoryType)
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{
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case kStronglyOrdered:
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entry.c = 0;
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entry.b = 0;
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entry.tex = 0;
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entry.s = 1; // Ignored
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break;
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case kDevice:
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if (isShareable)
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{
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entry.c = 0;
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entry.b = 1;
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entry.tex = 0;
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entry.s = 1; // Ignored
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}
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else
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{
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entry.c = 0;
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entry.b = 0;
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entry.tex = 2;
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entry.s = 0; // Ignored
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}
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break;
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case kOuterInner_WB_WA:
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entry.c = 1;
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entry.b = 1;
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entry.tex = 1;
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entry.s = isShareable;
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break;
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case kOuterInner_WT:
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entry.c = 1;
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entry.b = 0;
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entry.tex = 0;
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entry.s = isShareable;
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break;
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case kNoncacheable:
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entry.c = 0;
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entry.b = 0;
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entry.tex = 1;
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entry.s = isShareable;
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break;
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}
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// Set attributes from specified access mode.
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switch (access)
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{
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case kNoAccess:
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entry.ap2 = 0;
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entry.ap1_0 = 0;
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break;
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case kROAccess:
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entry.ap2 = 1;
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entry.ap1_0 = 3;
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break;
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case kRWAccess:
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entry.ap2 = 0;
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entry.ap1_0 = 3;
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break;
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}
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// Get the L1 page table base address.
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uint32_t * table = (uint32_t *)&__l1_page_table_start;
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// Convert addresses to 12-bit bases.
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uint32_t vbase = va >> kMMU_L1_Section_Address_Shift;
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uint32_t pbase = pa >> kMMU_L1_Section_Address_Shift;
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uint32_t entries = length >> kMMU_L1_Section_Address_Shift;
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// Fill in L1 page table entries.
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for (; entries > 0; ++pbase, ++vbase, --entries)
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{
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entry.address = pbase;
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table[vbase] = entry.u;
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}
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// Invalidate TLB
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arm_unified_tlb_invalidate();
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}
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bool mmu_virtual_to_physical(uint32_t virtualAddress, uint32_t * physicalAddress)
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{
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uint32_t pa = 0;
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// VA to PA translation with privileged read permission check
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_ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 0);
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// Read PA register
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_ARM_MRC(15, 0, pa, 7, 4, 0);
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// First bit of returned value is Result of conversion (0 is successful translation)
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if (pa & 1)
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{
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// We can try write permission also
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// VA to PA translation with privileged write permission check
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_ARM_MCR(15, 0, virtualAddress & 0xfffffc00, 7, 8, 1);
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// Read PA register
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_ARM_MRC(15, 0, pa, 7, 4, 0);
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// First bit of returned value is Result of conversion (0 is successful translation)
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if (pa & 1)
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{
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return false;
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}
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}
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if (physicalAddress)
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{
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// complete address returning base + offset
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pa = (pa & 0xfffff000) | (virtualAddress & 0x00000fff);
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*physicalAddress = pa;
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}
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return true;
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}
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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