318 lines
8.8 KiB
C
318 lines
8.8 KiB
C
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/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-03-19 WangHuachen the first version
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "gic.h"
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#include "drv_uart.h"
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#define IOU_SLCR_BASE_ADDR XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR
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#define ZynqMP_IOU_SLCR_MIO_PIN(x) (IOU_SLCR_BASE_ADDR + 0x04 * x)
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#define XUARTPS_MAX_RATE 921600U
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#define XUARTPS_MIN_RATE 110U
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#define XUARTPS_MAX_BAUD_ERROR_RATE 3U /* max % error allowed */
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#define ZynqMP_UART_INT_DISABLE(UART) \
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(UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL))
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#define ZynqMP_UART_INT_ENABLE(UART) \
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(UART->IER |= (UART_IXR_RXOVR | UART_IXR_RXFULL))
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#define ZynqMP_UART_SENDCHAR(UART, ch) \
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do { \
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while ((UART->SR) & UART_SR_TXFULL); \
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UART->FIFO = ch; \
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} while(0)
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#define ZynqMP_UART_GETCHAR(UART, ch) \
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do { \
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if (UART->ISR & UART_IXR_RXOVR) \
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{ \
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ch = UART->FIFO & 0xff; \
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UART->ISR = (UART_IXR_RXOVR | UART_IXR_RXFULL); \
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} \
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} while(0)
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static void UartEnable(UART_Registers* uart)
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{
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uint32_t tmp = uart->CR;
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tmp &= ~UART_CR_EN_DIS_MASK;
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tmp |= (UART_CR_TX_EN | UART_CR_RX_EN);
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uart->CR = tmp;
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}
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static void UartDisable(UART_Registers* uart)
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{
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uint32_t tmp = uart->CR;
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tmp &= ~UART_CR_EN_DIS_MASK;
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tmp |= (UART_CR_TX_DIS | UART_CR_RX_DIS);
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uart->CR = tmp;
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}
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static void UartResetTXRXLogic(UART_Registers* uart)
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{
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uart->CR |= (UART_CR_TXRST | UART_CR_RXRST);
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while (uart->CR & (UART_CR_TXRST | UART_CR_RXRST));
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}
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/* UART TxD/RxD | L3 Mux | L2 Mux | L1 Mux */
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#define RX_MIO_PIN_MODE ((0x6 << 5) | (0x0 << 3) | (0x0 << 2) | (0x0 << 1))
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#define TX_MIO_PIN_MODE ((0x6 << 5) | (0x0 << 3) | (0x0 << 2) | (0x0 << 1))
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struct hw_uart_device
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{
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UART_Registers * uart;
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rt_uint32_t irqno;
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rt_uint32_t inputClockHz;
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/* MIO pin mode address */
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rt_uint32_t *rxmio;
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rt_uint32_t *txmio;
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};
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/* RT-Thread UART interface */
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static void rt_hw_uart_isr(int irqno, void *param)
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{
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struct rt_serial_device *serial = (struct rt_serial_device *)param;
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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}
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static rt_err_t XUartPsSetBandRate(struct hw_uart_device *pdev, rt_uint32_t targetBandRate)
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{
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rt_uint32_t IterBAUDDIV; /* Iterator for available baud divisor values */
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rt_uint32_t BRGR_Value; /* Calculated value for baud rate generator */
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rt_uint32_t CalcBaudRate; /* Calculated baud rate */
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rt_uint32_t BaudError; /* Diff between calculated and requested baud rate */
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rt_uint32_t Best_BRGR = 0U; /* Best value for baud rate generator */
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rt_uint8_t Best_BAUDDIV = 0U; /* Best value for baud divisor */
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rt_uint32_t Best_Error = 0xFFFFFFFFU;
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rt_uint32_t PercentError;
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rt_uint32_t ModeReg;
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rt_uint32_t InputClk;
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if ((targetBandRate > (rt_uint32_t)XUARTPS_MAX_RATE) ||
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(targetBandRate < (rt_uint32_t)XUARTPS_MIN_RATE))
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return -RT_EINVAL;
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/*
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* Make sure the baud rate is not impossilby large.
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* Fastest possible baud rate is Input Clock / 2.
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*/
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if ((targetBandRate * 2) > pdev->inputClockHz)
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return -RT_EINVAL;
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/* Check whether the input clock is divided by 8 */
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ModeReg = pdev->uart->MR;
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InputClk = pdev->inputClockHz;
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if(ModeReg & UART_MR_CLKSEL)
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InputClk = pdev->inputClockHz / 8;
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/*
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* Determine the Baud divider. It can be 4to 254.
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* Loop through all possible combinations
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*/
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for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++)
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{
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/* Calculate the value for BRGR register */
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BRGR_Value = InputClk / (targetBandRate * (IterBAUDDIV + 1));
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/* Calculate the baud rate from the BRGR value */
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CalcBaudRate = InputClk / (BRGR_Value * (IterBAUDDIV + 1));
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/* Avoid unsigned integer underflow */
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if (targetBandRate > CalcBaudRate)
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BaudError = targetBandRate - CalcBaudRate;
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else
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BaudError = CalcBaudRate - targetBandRate;
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/* Find the calculated baud rate closest to requested baud rate. */
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if (Best_Error > BaudError)
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{
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Best_BRGR = BRGR_Value;
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Best_BAUDDIV = IterBAUDDIV;
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Best_Error = BaudError;
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}
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}
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/* Make sure the best error is not too large. */
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PercentError = (Best_Error * 100) / targetBandRate;
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if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError)
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return -RT_ERROR;
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pdev->uart->BAUDGEN = Best_BRGR;
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pdev->uart->BAUDDIV = Best_BAUDDIV;
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return RT_EOK;
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}
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static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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uint32_t mr;
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struct hw_uart_device *pdev = serial->parent.user_data;
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UART_Registers *uart = pdev->uart;
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UartDisable(uart);
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UartResetTXRXLogic(uart);
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UartEnable(uart);
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mr = uart->MR & ~(UART_MR_CHARLEN_MASK |
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UART_MR_STOPMODE_MASK |
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UART_MR_PARITY_MASK);
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if (cfg->stop_bits == STOP_BITS_2)
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mr |= UART_MR_STOPMODE_2_BIT;
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else if (cfg->stop_bits == STOP_BITS_1)
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mr |= UART_MR_STOPMODE_1_BIT;
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else
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return -RT_EINVAL;
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if (cfg->parity == PARITY_EVEN)
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mr |= UART_MR_PARITY_EVEN;
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else if (cfg->parity == PARITY_ODD)
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mr |= UART_MR_PARITY_ODD;
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else if (cfg->parity == PARITY_NONE)
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mr |= UART_MR_PARITY_NONE;
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else
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return -RT_EINVAL;
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if (cfg->data_bits == DATA_BITS_8)
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mr |= UART_MR_CHARLEN_8_BIT;
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else if (cfg->data_bits == DATA_BITS_7)
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mr |= UART_MR_CHARLEN_7_BIT;
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else if (cfg->data_bits == DATA_BITS_6)
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mr |= UART_MR_CHARLEN_6_BIT;
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else
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return -RT_EINVAL;
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uart->MR = mr;
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uart->TXWM = 8;
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uart->RXWM = 1;
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if (XUartPsSetBandRate(pdev, cfg->baud_rate) != RT_EOK)
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{
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rt_kprintf("baudrate %d not implemented yet\n", cfg->baud_rate);
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return -RT_EINVAL;
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}
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/* disable all interrupts */
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uart->IDR = UART_IXR_MASK;
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/* configure the pin */
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*(pdev->txmio) = TX_MIO_PIN_MODE;
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*(pdev->rxmio) = RX_MIO_PIN_MODE;
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return RT_EOK;
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}
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static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct hw_uart_device *pdev;
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RT_ASSERT(serial != RT_NULL);
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pdev = serial->parent.user_data;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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ZynqMP_UART_INT_DISABLE(pdev->uart);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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ZynqMP_UART_INT_ENABLE(pdev->uart);
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rt_hw_interrupt_install(pdev->irqno, rt_hw_uart_isr, serial, serial->parent.parent.name);
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/* set the interrupt to this cpu */
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arm_gic_set_cpu(0, pdev->irqno, 1 << rt_cpu_get_smp_id());
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rt_hw_interrupt_umask(pdev->irqno);
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break;
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}
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return RT_EOK;
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}
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static int uart_putc(struct rt_serial_device *serial, char c)
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{
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struct hw_uart_device *dev;
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RT_ASSERT(serial != RT_NULL);
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dev = (struct hw_uart_device *)serial->parent.user_data;
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ZynqMP_UART_SENDCHAR(dev->uart, c);
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return 1;
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}
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static int uart_getc(struct rt_serial_device *serial)
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{
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int ch;
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struct hw_uart_device *dev;
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RT_ASSERT(serial != RT_NULL);
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dev = (struct hw_uart_device *)serial->parent.user_data;
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ch = -1;
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ZynqMP_UART_GETCHAR(dev->uart, ch);
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return ch;
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}
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static const struct rt_uart_ops _uart_ops =
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{
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uart_configure,
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uart_control,
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uart_putc,
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uart_getc,
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};
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/* UART device driver structure */
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#ifdef BSP_USING_UART0
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static struct hw_uart_device _uart_device0 =
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{
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.uart = (UART_Registers*)XPAR_PSU_UART_0_BASEADDR,
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.irqno = XPAR_PSU_UART_0_INTR,
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.inputClockHz = XPAR_PSU_UART_0_UART_CLK_FREQ_HZ,
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.rxmio = (rt_uint32_t*)ZynqMP_IOU_SLCR_MIO_PIN(42), /* MIO42 */
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.txmio = (rt_uint32_t*)ZynqMP_IOU_SLCR_MIO_PIN(43), /* MIO43 */
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};
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static struct rt_serial_device _serial0;
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#endif
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int rt_hw_uart_init(void)
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{
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struct serial_configure config;
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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/* register uart device */
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#ifdef BSP_USING_UART0
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_serial0.ops = &_uart_ops;
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_serial0.config = config;
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rt_hw_serial_register(&_serial0, "uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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&_uart_device0);
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#endif
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return RT_EOK;
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}
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INIT_BOARD_EXPORT(rt_hw_uart_init);
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