883 lines
24 KiB
C
883 lines
24 KiB
C
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-14 luobeihai first version
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*/
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#include "board.h"
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#include "drv_sdio.h"
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#ifdef BSP_USING_SDIO
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//#define DRV_DEBUG
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#define LOG_TAG "drv.sdio"
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#include <drv_log.h>
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static struct apm32_sdio_config sdio_config = SDIO_BUS_CONFIG;
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static struct apm32_sdio_class sdio_obj;
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static struct rt_mmcsd_host *host;
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#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000)
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#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
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#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
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struct sdio_pkg
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{
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struct rt_mmcsd_cmd *cmd;
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void *buff;
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rt_uint32_t flag;
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};
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struct rthw_sdio
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{
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struct rt_mmcsd_host *host;
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struct apm32_sdio_des sdio_des;
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struct rt_event event;
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struct rt_mutex mutex;
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struct sdio_pkg *pkg;
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};
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rt_align(SDIO_ALIGN_LEN)
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static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
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static rt_uint32_t apm32_sdio_clk_get(struct apm32_sdio *hw_sdio)
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{
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return SDIO_CLOCK_FREQ;
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}
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/**
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* @brief This function get order from sdio.
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* @param data
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* @retval sdio order
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*/
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static int get_order(rt_uint32_t data)
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{
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int order = 0;
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switch (data)
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{
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case 1:
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order = 0;
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break;
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case 2:
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order = 1;
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break;
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case 4:
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order = 2;
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break;
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case 8:
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order = 3;
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break;
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case 16:
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order = 4;
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break;
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case 32:
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order = 5;
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break;
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case 64:
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order = 6;
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break;
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case 128:
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order = 7;
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break;
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case 256:
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order = 8;
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break;
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case 512:
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order = 9;
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break;
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case 1024:
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order = 10;
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break;
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case 2048:
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order = 11;
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break;
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case 4096:
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order = 12;
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break;
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case 8192:
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order = 13;
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break;
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case 16384:
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order = 14;
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break;
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default :
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order = 0;
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break;
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}
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return order;
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}
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/**
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* @brief This function wait sdio completed.
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* @param sdio rthw_sdio
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* @retval None
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*/
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static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
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{
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rt_uint32_t status;
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struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
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struct rt_mmcsd_data *data = cmd->data;
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struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
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if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
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rt_tick_from_millisecond(5000), &status) != RT_EOK)
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{
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LOG_E("wait completed timeout");
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cmd->err = -RT_ETIMEOUT;
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return;
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}
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if (sdio->pkg == RT_NULL)
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{
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return;
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}
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cmd->resp[0] = hw_sdio->resp1;
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cmd->resp[1] = hw_sdio->resp2;
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cmd->resp[2] = hw_sdio->resp3;
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cmd->resp[3] = hw_sdio->resp4;
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if (status & HW_SDIO_ERRORS)
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{
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if ((status & HW_SDIO_IT_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
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{
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cmd->err = RT_EOK;
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}
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else
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{
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cmd->err = -RT_ERROR;
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}
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if (status & HW_SDIO_IT_CTIMEOUT)
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{
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cmd->err = -RT_ETIMEOUT;
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}
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if (status & HW_SDIO_IT_DCRCFAIL)
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{
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data->err = -RT_ERROR;
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}
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if (status & HW_SDIO_IT_DTIMEOUT)
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{
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data->err = -RT_ETIMEOUT;
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}
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if (cmd->err == RT_EOK)
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{
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LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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else
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{
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LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
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status,
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status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "",
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status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "",
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status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "",
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status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "",
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status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "",
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status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "",
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status == 0 ? "NULL" : "",
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cmd->cmd_code,
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cmd->arg,
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data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
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data ? data->blks * data->blksize : 0,
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data ? data->blksize : 0
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);
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}
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}
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else
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{
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cmd->err = RT_EOK;
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LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
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}
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}
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/**
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* @brief This function transfer data by dma.
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* @param sdio rthw_sdio
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* @param pkg sdio package
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* @retval None
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*/
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static void rthw_sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
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{
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struct rt_mmcsd_data *data;
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int size;
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void *buff;
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struct apm32_sdio *hw_sdio;
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if ((RT_NULL == pkg) || (RT_NULL == sdio))
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{
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LOG_E("rthw_sdio_transfer_by_dma invalid args");
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return;
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}
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data = pkg->cmd->data;
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if (RT_NULL == data)
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{
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LOG_E("rthw_sdio_transfer_by_dma invalid args");
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return;
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}
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buff = pkg->buff;
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if (RT_NULL == buff)
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{
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LOG_E("rthw_sdio_transfer_by_dma invalid args");
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return;
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}
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hw_sdio = sdio->sdio_des.hw_sdio;
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size = data->blks * data->blksize;
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if (data->flags & DATA_DIR_WRITE)
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{
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sdio->sdio_des.txconfig((rt_uint32_t *)buff, (rt_uint32_t *)&hw_sdio->fifo, size);
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hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE;
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}
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else if (data->flags & DATA_DIR_READ)
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{
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sdio->sdio_des.rxconfig((rt_uint32_t *)&hw_sdio->fifo, (rt_uint32_t *)buff, size);
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hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE | HW_SDIO_DPSM_ENABLE;
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}
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}
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/**
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* @brief This function send command.
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* @param sdio rthw_sdio
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* @param pkg sdio package
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* @retval None
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*/
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static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
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{
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struct rt_mmcsd_cmd *cmd = pkg->cmd;
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struct rt_mmcsd_data *data = cmd->data;
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struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
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rt_uint32_t reg_cmd;
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/* save pkg */
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sdio->pkg = pkg;
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LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d",
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cmd->cmd_code,
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cmd->arg,
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resp_type(cmd) == RESP_NONE ? "NONE" : "",
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resp_type(cmd) == RESP_R1 ? "R1" : "",
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resp_type(cmd) == RESP_R1B ? "R1B" : "",
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resp_type(cmd) == RESP_R2 ? "R2" : "",
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resp_type(cmd) == RESP_R3 ? "R3" : "",
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resp_type(cmd) == RESP_R4 ? "R4" : "",
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resp_type(cmd) == RESP_R5 ? "R5" : "",
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resp_type(cmd) == RESP_R6 ? "R6" : "",
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resp_type(cmd) == RESP_R7 ? "R7" : "",
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data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
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data ? data->blks * data->blksize : 0,
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data ? data->blksize : 0
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);
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/* config cmd reg */
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reg_cmd = cmd->cmd_code | HW_SDIO_CPSM_ENABLE;
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if (resp_type(cmd) == RESP_NONE)
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reg_cmd |= HW_SDIO_RESPONSE_NO;
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else if (resp_type(cmd) == RESP_R2)
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reg_cmd |= HW_SDIO_RESPONSE_LONG;
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else
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reg_cmd |= HW_SDIO_RESPONSE_SHORT;
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/* config data reg */
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if (data != RT_NULL)
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{
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rt_uint32_t dir = 0;
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rt_uint32_t size = data->blks * data->blksize;
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int order;
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hw_sdio->dctrl = 0;
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hw_sdio->dtimer = HW_SDIO_DATATIMEOUT;
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hw_sdio->dlen = size;
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order = get_order(data->blksize);
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dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0;
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hw_sdio->dctrl = HW_SDIO_IO_ENABLE | (order << 4) | dir;
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}
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/* transfer config */
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if (data != RT_NULL)
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{
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rthw_sdio_transfer_by_dma(sdio, pkg);
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}
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/* open irq */
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hw_sdio->mask |= HW_SDIO_IT_CMDSENT | HW_SDIO_IT_CMDREND | HW_SDIO_ERRORS;
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if (data != RT_NULL)
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{
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hw_sdio->mask |= HW_SDIO_IT_DATAEND;
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}
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/* send cmd */
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hw_sdio->arg = cmd->arg;
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hw_sdio->cmd = reg_cmd;
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/* wait completed */
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rthw_sdio_wait_completed(sdio);
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/* Waiting for data to be sent to completion */
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if (data != RT_NULL)
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{
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volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
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while (count && (hw_sdio->sta & (HW_SDIO_IT_TXACT | HW_SDIO_IT_RXACT)))
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{
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count--;
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}
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if ((count == 0) || (hw_sdio->sta & HW_SDIO_ERRORS))
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{
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cmd->err = -RT_ERROR;
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}
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}
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/* close irq, keep sdio irq */
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hw_sdio->mask = hw_sdio->mask & HW_SDIO_IT_SDIOIT ? HW_SDIO_IT_SDIOIT : 0x00;
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/* clear pkg */
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sdio->pkg = RT_NULL;
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}
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/**
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* @brief This function send sdio request.
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* @param host rt_mmcsd_host
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* @param req request
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* @retval None
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*/
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static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct sdio_pkg pkg;
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struct rthw_sdio *sdio = host->private_data;
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struct rt_mmcsd_data *data;
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RTHW_SDIO_LOCK(sdio);
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if (req->cmd != RT_NULL)
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{
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rt_memset(&pkg, 0, sizeof(pkg));
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data = req->cmd->data;
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pkg.cmd = req->cmd;
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if (data != RT_NULL)
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{
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rt_uint32_t size = data->blks * data->blksize;
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RT_ASSERT(size <= SDIO_BUFF_SIZE);
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pkg.buff = data->buf;
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||
|
|
if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
|
||
|
|
{
|
||
|
|
pkg.buff = cache_buf;
|
||
|
|
if (data->flags & DATA_DIR_WRITE)
|
||
|
|
{
|
||
|
|
rt_memcpy(cache_buf, data->buf, size);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
rthw_sdio_send_command(sdio, &pkg);
|
||
|
|
|
||
|
|
if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
|
||
|
|
{
|
||
|
|
rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (req->stop != RT_NULL)
|
||
|
|
{
|
||
|
|
rt_memset(&pkg, 0, sizeof(pkg));
|
||
|
|
pkg.cmd = req->stop;
|
||
|
|
rthw_sdio_send_command(sdio, &pkg);
|
||
|
|
}
|
||
|
|
|
||
|
|
RTHW_SDIO_UNLOCK(sdio);
|
||
|
|
|
||
|
|
mmcsd_req_complete(sdio->host);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function config sdio.
|
||
|
|
* @param host rt_mmcsd_host
|
||
|
|
* @param io_cfg rt_mmcsd_io_cfg
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
|
||
|
|
{
|
||
|
|
rt_uint32_t clkcr, div, clk_src;
|
||
|
|
rt_uint32_t clk = io_cfg->clock;
|
||
|
|
struct rthw_sdio *sdio = host->private_data;
|
||
|
|
struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
|
||
|
|
|
||
|
|
clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
|
||
|
|
if (clk_src < 400 * 1000)
|
||
|
|
{
|
||
|
|
LOG_E("The clock rate is too low! rata:%d", clk_src);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (clk > host->freq_max) clk = host->freq_max;
|
||
|
|
|
||
|
|
if (clk > clk_src)
|
||
|
|
{
|
||
|
|
LOG_W("Setting rate is greater than clock source rate.");
|
||
|
|
clk = clk_src;
|
||
|
|
}
|
||
|
|
|
||
|
|
LOG_D("clk:%d width:%s%s%s power:%s%s%s",
|
||
|
|
clk,
|
||
|
|
io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
|
||
|
|
io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
|
||
|
|
io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
|
||
|
|
io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
|
||
|
|
io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
|
||
|
|
io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
|
||
|
|
);
|
||
|
|
|
||
|
|
RTHW_SDIO_LOCK(sdio);
|
||
|
|
|
||
|
|
div = clk_src / clk;
|
||
|
|
if ((clk == 0) || (div == 0))
|
||
|
|
{
|
||
|
|
clkcr = 0;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if (div < 2)
|
||
|
|
{
|
||
|
|
div = 2;
|
||
|
|
}
|
||
|
|
else if (div > 0xFF)
|
||
|
|
{
|
||
|
|
div = 0xFF;
|
||
|
|
}
|
||
|
|
div -= 2;
|
||
|
|
clkcr = div | HW_SDIO_CLK_ENABLE;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
|
||
|
|
{
|
||
|
|
clkcr |= HW_SDIO_BUSWIDE_8B;
|
||
|
|
}
|
||
|
|
else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
|
||
|
|
{
|
||
|
|
clkcr |= HW_SDIO_BUSWIDE_4B;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
clkcr |= HW_SDIO_BUSWIDE_1B;
|
||
|
|
}
|
||
|
|
|
||
|
|
hw_sdio->clkcr = clkcr;
|
||
|
|
|
||
|
|
switch (io_cfg->power_mode)
|
||
|
|
{
|
||
|
|
case MMCSD_POWER_OFF:
|
||
|
|
hw_sdio->power = HW_SDIO_POWER_OFF;
|
||
|
|
break;
|
||
|
|
case MMCSD_POWER_UP:
|
||
|
|
hw_sdio->power = HW_SDIO_POWER_UP;
|
||
|
|
break;
|
||
|
|
case MMCSD_POWER_ON:
|
||
|
|
hw_sdio->power = HW_SDIO_POWER_ON;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
LOG_W("unknown power_mode %d", io_cfg->power_mode);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
RTHW_SDIO_UNLOCK(sdio);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function update sdio interrupt.
|
||
|
|
* @param host rt_mmcsd_host
|
||
|
|
* @param enable
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
|
||
|
|
{
|
||
|
|
struct rthw_sdio *sdio = host->private_data;
|
||
|
|
struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
|
||
|
|
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
LOG_D("enable sdio irq");
|
||
|
|
hw_sdio->mask |= HW_SDIO_IT_SDIOIT;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
LOG_D("disable sdio irq");
|
||
|
|
hw_sdio->mask &= ~HW_SDIO_IT_SDIOIT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function detect sdcard.
|
||
|
|
* @param host rt_mmcsd_host
|
||
|
|
* @retval 0x01
|
||
|
|
*/
|
||
|
|
static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
|
||
|
|
{
|
||
|
|
LOG_D("try to detect device");
|
||
|
|
return 0x01;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function interrupt process function.
|
||
|
|
* @param host rt_mmcsd_host
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
|
||
|
|
{
|
||
|
|
int complete = 0;
|
||
|
|
struct rthw_sdio *sdio = host->private_data;
|
||
|
|
struct apm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
|
||
|
|
rt_uint32_t intstatus = hw_sdio->sta;
|
||
|
|
|
||
|
|
if (intstatus & HW_SDIO_ERRORS)
|
||
|
|
{
|
||
|
|
hw_sdio->icr = HW_SDIO_ERRORS;
|
||
|
|
complete = 1;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
if (intstatus & HW_SDIO_IT_CMDREND)
|
||
|
|
{
|
||
|
|
hw_sdio->icr = HW_SDIO_IT_CMDREND;
|
||
|
|
|
||
|
|
if (sdio->pkg != RT_NULL)
|
||
|
|
{
|
||
|
|
if (!sdio->pkg->cmd->data)
|
||
|
|
{
|
||
|
|
complete = 1;
|
||
|
|
}
|
||
|
|
else if ((sdio->pkg->cmd->data->flags & DATA_DIR_WRITE))
|
||
|
|
{
|
||
|
|
hw_sdio->dctrl |= HW_SDIO_DPSM_ENABLE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (intstatus & HW_SDIO_IT_CMDSENT)
|
||
|
|
{
|
||
|
|
hw_sdio->icr = HW_SDIO_IT_CMDSENT;
|
||
|
|
|
||
|
|
if (resp_type(sdio->pkg->cmd) == RESP_NONE)
|
||
|
|
{
|
||
|
|
complete = 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (intstatus & HW_SDIO_IT_DATAEND)
|
||
|
|
{
|
||
|
|
hw_sdio->icr = HW_SDIO_IT_DATAEND;
|
||
|
|
complete = 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if ((intstatus & HW_SDIO_IT_SDIOIT) && (hw_sdio->mask & HW_SDIO_IT_SDIOIT))
|
||
|
|
{
|
||
|
|
hw_sdio->icr = HW_SDIO_IT_SDIOIT;
|
||
|
|
sdio_irq_wakeup(host);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (complete)
|
||
|
|
{
|
||
|
|
hw_sdio->mask &= ~HW_SDIO_ERRORS;
|
||
|
|
rt_event_send(&sdio->event, intstatus);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_mmcsd_host_ops ops =
|
||
|
|
{
|
||
|
|
rthw_sdio_request,
|
||
|
|
rthw_sdio_iocfg,
|
||
|
|
rthw_sd_detect,
|
||
|
|
rthw_sdio_irq_update,
|
||
|
|
};
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function create mmcsd host.
|
||
|
|
* @param sdio_des apm32_sdio_des
|
||
|
|
* @retval rt_mmcsd_host
|
||
|
|
*/
|
||
|
|
struct rt_mmcsd_host *sdio_host_create(struct apm32_sdio_des *sdio_des)
|
||
|
|
{
|
||
|
|
struct rt_mmcsd_host *host;
|
||
|
|
struct rthw_sdio *sdio = RT_NULL;
|
||
|
|
|
||
|
|
if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
|
||
|
|
{
|
||
|
|
LOG_E("L:%d F:%s %s %s %s",
|
||
|
|
(sdio_des == RT_NULL ? "sdio_des is NULL" : ""),
|
||
|
|
(sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""),
|
||
|
|
(sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")
|
||
|
|
);
|
||
|
|
return RT_NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
sdio = rt_malloc(sizeof(struct rthw_sdio));
|
||
|
|
if (sdio == RT_NULL)
|
||
|
|
{
|
||
|
|
LOG_E("L:%d F:%s malloc rthw_sdio fail");
|
||
|
|
return RT_NULL;
|
||
|
|
}
|
||
|
|
rt_memset(sdio, 0, sizeof(struct rthw_sdio));
|
||
|
|
|
||
|
|
host = mmcsd_alloc_host();
|
||
|
|
if (host == RT_NULL)
|
||
|
|
{
|
||
|
|
LOG_E("L:%d F:%s mmcsd alloc host fail");
|
||
|
|
rt_free(sdio);
|
||
|
|
return RT_NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct apm32_sdio_des));
|
||
|
|
sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? (struct apm32_sdio *)SDIO_BASE_ADDRESS : sdio_des->hw_sdio);
|
||
|
|
sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? apm32_sdio_clk_get : sdio_des->clk_get);
|
||
|
|
|
||
|
|
rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
|
||
|
|
rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_PRIO);
|
||
|
|
|
||
|
|
/* set host defautl attributes */
|
||
|
|
host->ops = &ops;
|
||
|
|
host->freq_min = 400 * 1000;
|
||
|
|
host->freq_max = SDIO_MAX_FREQ;
|
||
|
|
host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
|
||
|
|
#ifndef SDIO_USING_1_BIT
|
||
|
|
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
|
||
|
|
#else
|
||
|
|
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
|
||
|
|
#endif
|
||
|
|
host->max_seg_size = SDIO_BUFF_SIZE;
|
||
|
|
host->max_dma_segs = 1;
|
||
|
|
host->max_blk_size = 512;
|
||
|
|
host->max_blk_count = 512;
|
||
|
|
|
||
|
|
/* link up host and sdio */
|
||
|
|
sdio->host = host;
|
||
|
|
host->private_data = sdio;
|
||
|
|
|
||
|
|
rthw_sdio_irq_update(host, 1);
|
||
|
|
|
||
|
|
/* ready to change */
|
||
|
|
mmcsd_change(host);
|
||
|
|
|
||
|
|
return host;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function configures the DMATX.
|
||
|
|
* @param BufferSRC: pointer to the source buffer
|
||
|
|
* @param BufferSize: buffer size
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
|
||
|
|
{
|
||
|
|
DMA_Config_T DMA_InitStructure;
|
||
|
|
static uint32_t size = 0;
|
||
|
|
|
||
|
|
size += BufferSize * 4;
|
||
|
|
sdio_obj.cfg = &sdio_config;
|
||
|
|
sdio_obj.dma.handle_tx = sdio_config.dma_tx.Instance;
|
||
|
|
|
||
|
|
#if defined (SOC_SERIES_APM32F1)
|
||
|
|
/* clear DMA flag */
|
||
|
|
DMA_ClearStatusFlag(DMA2_FLAG_GINT4 | DMA2_FLAG_TC4 | DMA2_FLAG_HT4 | DMA2_FLAG_TERR4);
|
||
|
|
|
||
|
|
/* Disable DMA */
|
||
|
|
DMA_Disable(sdio_obj.dma.handle_rx);
|
||
|
|
|
||
|
|
DMA_InitStructure.dir = DMA_DIR_PERIPHERAL_DST;
|
||
|
|
DMA_InitStructure.bufferSize = BufferSize;
|
||
|
|
DMA_InitStructure.memoryBaseAddr = (uint32_t)src;
|
||
|
|
DMA_InitStructure.memoryDataSize = DMA_MEMORY_DATA_SIZE_WOED;
|
||
|
|
DMA_InitStructure.memoryInc = DMA_MEMORY_INC_ENABLE;
|
||
|
|
DMA_InitStructure.peripheralBaseAddr = (uint32_t)dst;
|
||
|
|
DMA_InitStructure.peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_WOED;
|
||
|
|
DMA_InitStructure.peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
|
||
|
|
DMA_InitStructure.priority = DMA_PRIORITY_MEDIUM;
|
||
|
|
DMA_InitStructure.loopMode = DMA_MODE_NORMAL;
|
||
|
|
DMA_InitStructure.M2M = DMA_M2MEN_DISABLE;
|
||
|
|
|
||
|
|
DMA_Config(sdio_obj.dma.handle_tx, &DMA_InitStructure);
|
||
|
|
|
||
|
|
DMA_Enable(sdio_obj.dma.handle_tx);
|
||
|
|
#elif defined (SOC_SERIES_APM32F4)
|
||
|
|
/* Wait DMA can be setting */
|
||
|
|
while (DMA_ReadCmdStatus(sdio_obj.dma.handle_tx) != DISABLE);
|
||
|
|
|
||
|
|
/* Clear all DMA intrrupt flag */
|
||
|
|
DMA_Reset(sdio_obj.dma.handle_tx);
|
||
|
|
|
||
|
|
DMA_InitStructure.channel = sdio_config.dma_tx.channel;
|
||
|
|
DMA_InitStructure.dir = DMA_DIR_MEMORYTOPERIPHERAL;
|
||
|
|
DMA_InitStructure.bufferSize = BufferSize;
|
||
|
|
DMA_InitStructure.memoryBaseAddr = (uint32_t)src;
|
||
|
|
DMA_InitStructure.memoryDataSize = DMA_MEMORY_DATA_SIZE_WORD;
|
||
|
|
DMA_InitStructure.memoryInc = DMA_MEMORY_INC_ENABLE;
|
||
|
|
DMA_InitStructure.memoryBurst = DMA_MEMORYBURST_INC4;
|
||
|
|
DMA_InitStructure.peripheralBaseAddr = (uint32_t)dst;
|
||
|
|
DMA_InitStructure.peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_WORD;
|
||
|
|
DMA_InitStructure.peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
|
||
|
|
DMA_InitStructure.peripheralBurst = DMA_PERIPHERALBURST_INC4;
|
||
|
|
DMA_InitStructure.loopMode = DMA_MODE_NORMAL;
|
||
|
|
DMA_InitStructure.priority = DMA_PRIORITY_MEDIUM;
|
||
|
|
DMA_InitStructure.fifoMode = DMA_FIFOMODE_ENABLE;
|
||
|
|
DMA_InitStructure.fifoThreshold = DMA_FIFOTHRESHOLD_FULL;
|
||
|
|
|
||
|
|
DMA_Config(sdio_obj.dma.handle_tx, &DMA_InitStructure);
|
||
|
|
DMA_ConfigFlowController(sdio_obj.dma.handle_tx, DMA_FLOWCTRL_PERIPHERAL);
|
||
|
|
DMA_Enable(sdio_obj.dma.handle_tx);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function configures the DMARX.
|
||
|
|
* @param BufferDST: pointer to the destination buffer
|
||
|
|
* @param BufferSize: buffer size
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
|
||
|
|
{
|
||
|
|
DMA_Config_T DMA_InitStructure;
|
||
|
|
|
||
|
|
sdio_obj.cfg = &sdio_config;
|
||
|
|
sdio_obj.dma.handle_rx = sdio_config.dma_rx.Instance;
|
||
|
|
|
||
|
|
#if defined (SOC_SERIES_APM32F1)
|
||
|
|
/* clear DMA flag */
|
||
|
|
DMA_ClearStatusFlag(DMA2_FLAG_GINT4 | DMA2_FLAG_TC4 | DMA2_FLAG_HT4 | DMA2_FLAG_TERR4);
|
||
|
|
|
||
|
|
/* Disable DMA */
|
||
|
|
DMA_Disable(sdio_obj.dma.handle_rx);
|
||
|
|
|
||
|
|
DMA_InitStructure.dir = DMA_DIR_PERIPHERAL_SRC;
|
||
|
|
DMA_InitStructure.bufferSize = BufferSize;
|
||
|
|
DMA_InitStructure.memoryBaseAddr = (uint32_t)dst;
|
||
|
|
DMA_InitStructure.memoryDataSize = DMA_MEMORY_DATA_SIZE_WOED;
|
||
|
|
DMA_InitStructure.memoryInc = DMA_MEMORY_INC_ENABLE;
|
||
|
|
DMA_InitStructure.peripheralBaseAddr = (uint32_t)src;
|
||
|
|
DMA_InitStructure.peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_WOED;
|
||
|
|
DMA_InitStructure.peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
|
||
|
|
DMA_InitStructure.priority = DMA_PRIORITY_MEDIUM;
|
||
|
|
DMA_InitStructure.loopMode = DMA_MODE_NORMAL;
|
||
|
|
DMA_InitStructure.M2M = DMA_M2MEN_DISABLE;
|
||
|
|
|
||
|
|
DMA_Config(sdio_obj.dma.handle_rx, &DMA_InitStructure);
|
||
|
|
|
||
|
|
DMA_Enable(sdio_obj.dma.handle_rx);
|
||
|
|
#elif defined (SOC_SERIES_APM32F4)
|
||
|
|
/* Wait DMA can be setting */
|
||
|
|
while (DMA_ReadCmdStatus(sdio_obj.dma.handle_rx) != DISABLE);
|
||
|
|
|
||
|
|
/* Clear all DMA intrrupt flag */
|
||
|
|
DMA_Reset(sdio_obj.dma.handle_rx);
|
||
|
|
|
||
|
|
DMA_InitStructure.channel = sdio_config.dma_rx.channel;
|
||
|
|
DMA_InitStructure.dir = DMA_DIR_PERIPHERALTOMEMORY;
|
||
|
|
DMA_InitStructure.bufferSize = BufferSize;
|
||
|
|
DMA_InitStructure.memoryBaseAddr = (uint32_t)dst;
|
||
|
|
DMA_InitStructure.memoryDataSize = DMA_MEMORY_DATA_SIZE_WORD;
|
||
|
|
DMA_InitStructure.memoryInc = DMA_MEMORY_INC_ENABLE;
|
||
|
|
DMA_InitStructure.memoryBurst = DMA_MEMORYBURST_INC4;
|
||
|
|
DMA_InitStructure.peripheralBaseAddr = (uint32_t)src;
|
||
|
|
DMA_InitStructure.peripheralDataSize = DMA_PERIPHERAL_DATA_SIZE_WORD;
|
||
|
|
DMA_InitStructure.peripheralInc = DMA_PERIPHERAL_INC_DISABLE;
|
||
|
|
DMA_InitStructure.peripheralBurst = DMA_PERIPHERALBURST_INC4;
|
||
|
|
DMA_InitStructure.loopMode = DMA_MODE_NORMAL;
|
||
|
|
DMA_InitStructure.priority = DMA_PRIORITY_MEDIUM;
|
||
|
|
DMA_InitStructure.fifoMode = DMA_FIFOMODE_ENABLE;
|
||
|
|
DMA_InitStructure.fifoThreshold = DMA_FIFOTHRESHOLD_FULL;
|
||
|
|
|
||
|
|
DMA_Config(sdio_obj.dma.handle_rx, &DMA_InitStructure);
|
||
|
|
DMA_ConfigFlowController(sdio_obj.dma.handle_rx, DMA_FLOWCTRL_PERIPHERAL);
|
||
|
|
DMA_Enable(sdio_obj.dma.handle_rx);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function get apm32 sdio clock.
|
||
|
|
* @param hw_sdio: apm32_sdio
|
||
|
|
* @retval PCLK2Freq
|
||
|
|
*/
|
||
|
|
static rt_uint32_t apm32_sdio_clock_get(struct apm32_sdio *hw_sdio)
|
||
|
|
{
|
||
|
|
return RCM_ReadHCLKFreq();
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t DMA_TxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size)
|
||
|
|
{
|
||
|
|
SD_LowLevel_DMA_TxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4);
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t DMA_RxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size)
|
||
|
|
{
|
||
|
|
SD_LowLevel_DMA_RxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4);
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
void SDIO_IRQHandler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
/* Process All SDIO Interrupt Sources */
|
||
|
|
rthw_sdio_irq_process(host);
|
||
|
|
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
int rt_hw_sdio_init(void)
|
||
|
|
{
|
||
|
|
struct apm32_sdio_des sdio_des;
|
||
|
|
struct apm32_sdio_config hsd;
|
||
|
|
|
||
|
|
hsd.Instance = SDCARD_INSTANCE;
|
||
|
|
|
||
|
|
/* enable DMA clock */
|
||
|
|
#if defined (SOC_SERIES_APM32F1)
|
||
|
|
SET_BIT(RCM->AHBCLKEN, sdio_config.dma_rx.dma_rcm);
|
||
|
|
#elif defined (SOC_SERIES_APM32F4)
|
||
|
|
SET_BIT(RCM->AHB1CLKEN, sdio_config.dma_rx.dma_rcm);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
NVIC_EnableIRQRequest(SDIO_IRQn, 2, 0);
|
||
|
|
|
||
|
|
/* apm32 sdio gpio init and enable clock */
|
||
|
|
extern void apm32_msp_sdio_init(void *Instance);
|
||
|
|
apm32_msp_sdio_init((void *)(hsd.Instance));
|
||
|
|
|
||
|
|
sdio_des.clk_get = apm32_sdio_clock_get;
|
||
|
|
sdio_des.hw_sdio = (struct apm32_sdio *)SDCARD_INSTANCE;
|
||
|
|
sdio_des.rxconfig = DMA_RxConfig;
|
||
|
|
sdio_des.txconfig = DMA_TxConfig;
|
||
|
|
|
||
|
|
host = sdio_host_create(&sdio_des);
|
||
|
|
if (host == RT_NULL)
|
||
|
|
{
|
||
|
|
LOG_E("host create fail");
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
|
||
|
|
|
||
|
|
void apm32_mmcsd_change(void)
|
||
|
|
{
|
||
|
|
mmcsd_change(host);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|