288 lines
8.7 KiB
C
288 lines
8.7 KiB
C
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/*
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* drv_sfc.h
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*
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* Created on: 2016<EFBFBD><EFBFBD>4<EFBFBD><EFBFBD>5<EFBFBD><EFBFBD>
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* Author: Urey
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*/
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#ifndef DRIVER_DRV_SFC_H_
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#define DRIVER_DRV_SFC_H_
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#include <stdint.h>
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#define SFC_USE_SWAP
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#define SFC_USE_DMA
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#define SFC_USE_QUAD
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#define UNCACHE(addr) ((((uint32_t)(addr)) | 0xa0000000))
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/* SFC register */
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#define SFC_GLB (0x0000)
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#define SFC_DEV_CONF (0x0004)
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#define SFC_DEV_STA_EXP (0x0008)
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#define SFC_DEV_STA_RT (0x000c)
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#define SFC_DEV_STA_MSK (0x0010)
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#define SFC_TRAN_CONF(n) (0x0014 + (n * 4))
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#define SFC_TRAN_LEN (0x002c)
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#define SFC_DEV_ADDR(n) (0x0030 + (n * 4))
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#define SFC_DEV_ADDR_PLUS(n) (0x0048 + (n * 4))
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#define SFC_MEM_ADDR (0x0060)
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#define SFC_TRIG (0x0064)
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#define SFC_SR (0x0068)
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#define SFC_SCR (0x006c)
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#define SFC_INTC (0x0070)
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#define SFC_FSM (0x0074)
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#define SFC_CGE (0x0078)
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#define SFC_RM_DR (0x1000)
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/* For SFC_GLB */
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#define GLB_TRAN_DIR (1 << 13)
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#define GLB_TRAN_DIR_WRITE (1)
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#define GLB_TRAN_DIR_READ (0)
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#define GLB_THRESHOLD_OFFSET (7)
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#define GLB_THRESHOLD_MSK (0x3f << GLB_THRESHOLD_OFFSET)
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#define GLB_OP_MODE (1 << 6)
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#define SLAVE_MODE (0x0)
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#define DMA_MODE (0x1)
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#define GLB_PHASE_NUM_OFFSET (3)
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#define GLB_PHASE_NUM_MSK (0x7 << GLB_PHASE_NUM_OFFSET)
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#define GLB_WP_EN (1 << 2)
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#define GLB_BURST_MD_OFFSET (0)
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#define GLB_BURST_MD_MSK (0x3 << GLB_BURST_MD_OFFSET)
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/* For SFC_DEV_CONF */
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#define DEV_CONF_ONE_AND_HALF_CYCLE_DELAY (3)
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#define DEV_CONF_ONE_CYCLE_DELAY (2)
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#define DEV_CONF_HALF_CYCLE_DELAY (1)
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#define DEV_CONF_NO_DELAY (0)
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#define DEV_CONF_SMP_DELAY_OFFSET (16)
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#define DEV_CONF_SMP_DELAY_MSK (0x3 << DEV_CONF_SMP_DELAY_OFFSET)
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#define DEV_CONF_CMD_TYPE (0x1 << 15)
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#define DEV_CONF_STA_TYPE_OFFSET (13)
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#define DEV_CONF_STA_TYPE_MSK (0x1 << DEV_CONF_STA_TYPE_OFFSET)
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#define DEV_CONF_THOLD_OFFSET (11)
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#define DEV_CONF_THOLD_MSK (0x3 << DEV_CONF_THOLD_OFFSET)
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#define DEV_CONF_TSETUP_OFFSET (9)
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#define DEV_CONF_TSETUP_MSK (0x3 << DEV_CONF_TSETUP_OFFSET)
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#define DEV_CONF_TSH_OFFSET (5)
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#define DEV_CONF_TSH_MSK (0xf << DEV_CONF_TSH_OFFSET)
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#define DEV_CONF_CPHA (0x1 << 4)
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#define DEV_CONF_CPOL (0x1 << 3)
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#define DEV_CONF_CEDL (0x1 << 2)
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#define DEV_CONF_HOLDDL (0x1 << 1)
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#define DEV_CONF_WPDL (0x1 << 0)
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/* For SFC_TRAN_CONF */
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#define TRAN_CONF_TRAN_MODE_OFFSET (29)
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#define TRAN_CONF_TRAN_MODE_MSK (0x7)
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#define TRAN_CONF_ADDR_WIDTH_OFFSET (26)
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#define TRAN_CONF_ADDR_WIDTH_MSK (0x7 << ADDR_WIDTH_OFFSET)
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#define TRAN_CONF_POLLEN (1 << 25)
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#define TRAN_CONF_CMDEN (1 << 24)
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#define TRAN_CONF_FMAT (1 << 23)
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#define TRAN_CONF_DMYBITS_OFFSET (17)
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#define TRAN_CONF_DMYBITS_MSK (0x3f << DMYBITS_OFFSET)
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#define TRAN_CONF_DATEEN (1 << 16)
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#define TRAN_CONF_CMD_OFFSET (0)
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#define TRAN_CONF_CMD_MSK (0xffff << CMD_OFFSET)
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#define TRAN_CONF_CMD_LEN (1 << 15)
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/* For SFC_TRIG */
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#define TRIG_FLUSH (1 << 2)
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#define TRIG_STOP (1 << 1)
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#define TRIG_START (1 << 0)
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/* For SFC_SCR */
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#define CLR_END (1 << 4)
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#define CLR_TREQ (1 << 3)
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#define CLR_RREQ (1 << 2)
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#define CLR_OVER (1 << 1)
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#define CLR_UNDER (1 << 0)
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/* For SFC_TRAN_CONFx */
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#define TRAN_MODE_OFFSET (29)
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#define TRAN_MODE_MSK (0x7 << TRAN_MODE_OFFSET)
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#define TRAN_SPI_STANDARD (0x0)
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#define TRAN_SPI_DUAL (0x1 )
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#define TRAN_SPI_QUAD (0x5 )
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#define TRAN_SPI_IO_QUAD (0x6 )
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#define ADDR_WIDTH_OFFSET (26)
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#define ADDR_WIDTH_MSK (0x7 << ADDR_WIDTH_OFFSET)
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#define POLLEN (1 << 25)
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#define CMDEN (1 << 24)
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#define FMAT (1 << 23)
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#define DMYBITS_OFFSET (17)
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#define DMYBITS_MSK (0x3f << DMYBITS_OFFSET)
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#define DATEEN (1 << 16)
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#define CMD_OFFSET (0)
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#define CMD_MSK (0xffff << CMD_OFFSET)
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#define N_MAX 6
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#define MAX_SEGS 128
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#define CHANNEL_0 0
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#define CHANNEL_1 1
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#define CHANNEL_2 2
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#define CHANNEL_3 3
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#define CHANNEL_4 4
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#define CHANNEL_5 5
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#define ENABLE 1
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#define DISABLE 0
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#define COM_CMD 1 // common cmd
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#define POLL_CMD 2 // the cmd will poll the status of flash,ext: read status
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#define DMA_OPS 1
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#define CPU_OPS 0
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#define TM_STD_SPI 0
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#define TM_DI_DO_SPI 1
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#define TM_DIO_SPI 2
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#define TM_FULL_DIO_SPI 3
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#define TM_QI_QO_SPI 5
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#define TM_QIO_SPI 6
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#define TM_FULL_QIO_SPI 7
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#define DEFAULT_ADDRSIZE 3
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#ifndef max
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#define max(a, b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef min
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#define min(a, b) (((a) < (b)) ? (a) : (b))
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#endif
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/*SPI NOR FLASH Instructions*/
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#define CMD_WREN 0x06 /* Write Enable */
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#define CMD_WRDI 0x04 /* Write Disable */
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#define CMD_RDSR 0x05 /* Read Status Register */
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#define CMD_RDSR_1 0x35 /* Read Status1 Register */
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#define CMD_RDSR_2 0x15 /* Read Status2 Register */
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#define CMD_WRSR 0x01 /* Write Status Register */
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#define CMD_WRSR_1 0x31 /* Write Status1 Register */
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#define CMD_WRSR_2 0x11 /* Write Status2 Register */
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#define CMD_READ 0x03 /* Read Data */
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#define CMD_DUAL_READ 0x3b /* DUAL Read Data */
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#define CMD_QUAD_READ 0x6b /* QUAD Read Data */
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#define CMD_QUAD_IO_FAST_READ 0xeb /* QUAD FAST Read Data */
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#define CMD_QUAD_IO_WORD_FAST_READ 0xe7 /* QUAD IO WORD Read Data */
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#define CMD_FAST_READ 0x0B /* Read Data at high speed */
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#define CMD_PP 0x02 /* Page Program(write data) */
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#define CMD_QPP 0x32 /* QUAD Page Program(write data) */
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#define CMD_BE_4K 0x20
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#define CMD_BE_32K 0x52 /* Block Erase */
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#define CMD_BE_64K 0XD8 /* Block Erase */
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#define CMD_CE 0xC7 /* Bulk or Chip Erase */
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#define CMD_DP 0xB9 /* Deep Power-Down */
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#define CMD_RES 0xAB /* Release from Power-Down and Read Electronic Signature */
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#define CMD_REMS 0x90 /* Read Manufacture ID/ Device ID */
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#define CMD_RDID 0x9F /* Read Identification */
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#define CMD_NON 0x00 /* Read Identification */
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#define CMD_RUID 0x4B /* ReadUnique ID */
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#define CMD_NON 0x00 /* Read Identification */
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#define CMD_EN4B 0xB7 /* Enter 4 bytes address mode */
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#define CMD_EX4B 0xE9 /* Exit 4 bytes address mode */
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struct cmd_info
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{
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uint32_t cmd;
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uint32_t cmd_len;/*reserved; not use*/
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uint32_t dataen;
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uint32_t sta_exp;
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uint32_t sta_msk;
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};
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struct sfc_transfer
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{
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uint32_t direction;
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struct cmd_info *cmd_info;
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uint32_t addr_len;
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uint32_t addr;
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uint32_t addr_plus;
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uint32_t addr_dummy_bits;/*cmd + addr_dummy_bits + addr*/
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const uint8_t *data;
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uint32_t data_dummy_bits;/*addr + data_dummy_bits + data*/
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uint32_t len;
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uint32_t cur_len;
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uint32_t sfc_mode;
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uint32_t ops_mode;
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uint32_t phase_format;/*we just use default value;phase1:cmd+dummy+addr... phase0:cmd+addr+dummy...*/
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rt_list_t transfer_list;
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};
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struct sfc_message
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{
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rt_list_t transfers;
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uint32_t actual_length;
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uint32_t status;
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};
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struct sfc
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{
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void *iomem;
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int irq;
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struct clk *clk;
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struct clk *clk_gate;
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uint32_t src_clk;
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uint32_t threshold;
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struct sfc_transfer *transfer;
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struct rt_completion done;
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};
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struct sfc_quad_mode
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{
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uint8_t RDSR_CMD;
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uint32_t RD_DATE_SIZE;//the data is write the spi status register for QE bit
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uint8_t sfc_mode;
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uint8_t WRSR_CMD;
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uint32_t WD_DATE_SIZE;//the data is write the spi status register for QE bit
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uint8_t cmd_read;
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uint32_t RDSR_DATE;//the data is write the spi status register for QE bit
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uint32_t WRSR_DATE;//this bit should be the flash QUAD mode enable
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uint32_t dummy_byte;
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};
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struct sfc_flash
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{
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struct rt_mtd_nor_device mtd;
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char *name;
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uint32_t id;
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uint8_t uid[8];
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uint32_t pagesize;
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uint32_t sectorsize;
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uint32_t chipsize;
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uint32_t erasesize;
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uint32_t writesize;
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uint32_t addrsize;
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struct sfc *sfc;
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uint32_t sfc_mode;
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#ifdef SFC_USE_QUAD
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struct sfc_quad_mode *quad_mode;
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#endif
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struct rt_mutex lock;
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};
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int sfc_norflash_probe(struct sfc_flash *flash);
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size_t sfc_norflash_read(struct sfc_flash *flash, rt_off_t from, uint8_t *buf, size_t len);
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size_t sfc_norflash_write(struct sfc_flash *flash, rt_off_t to, const uint8_t *buf, size_t len);
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int sfc_norflash_erase_sector(struct sfc_flash *flash, uint32_t addr);
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int sfc_norflash_set_addr_width_4byte(struct sfc_flash *flash,int on);
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#endif /* DRIVER_DRV_SFC_H_ */
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