213 lines
9.0 KiB
C
213 lines
9.0 KiB
C
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_xbara.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the XBARA instance from peripheral base address.
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*
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* @param base XBARA peripheral base address.
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* @return XBARA instance.
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*/
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static uint32_t XBARA_GetInstance(XBARA_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Array of XBARA peripheral base address. */
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static XBARA_Type *const s_xbaraBases[] = XBARA_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Array of XBARA clock name. */
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static const clock_ip_name_t s_xbaraClock[] = XBARA_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t XBARA_GetInstance(XBARA_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_xbaraBases); instance++)
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{
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if (s_xbaraBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_xbaraBases));
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return instance;
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}
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void XBARA_Init(XBARA_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable XBARA module clock. */
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CLOCK_EnableClock(s_xbaraClock[XBARA_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void XBARA_Deinit(XBARA_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable XBARA module clock. */
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CLOCK_DisableClock(s_xbaraClock[XBARA_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output)
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{
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XBARA_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU));
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}
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uint32_t XBARA_GetStatusFlags(XBARA_Type *base)
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{
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uint32_t status_flag;
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status_flag = ((base->CTRL0 & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)) |
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((base->CTRL1 & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)) << 16U));
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return status_flag;
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}
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void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask)
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{
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uint16_t regVal;
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/* Assign regVal to CTRL0 register's value */
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regVal = (base->CTRL0);
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/* Perform this command to avoid writing 1 into interrupt flag bits */
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regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
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/* Write 1 to interrupt flag bits corresponding to mask */
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regVal |= (uint16_t)(mask & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
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/* Write regVal value into CTRL0 register */
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base->CTRL0 = regVal;
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/* Assign regVal to CTRL1 register's value */
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regVal = (base->CTRL1);
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/* Perform this command to avoid writing 1 into interrupt flag bits */
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regVal &= (uint16_t)(~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK));
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/* Write 1 to interrupt flag bits corresponding to mask */
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regVal |= (uint16_t)((mask >> 16U) & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK));
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/* Write regVal value into CTRL1 register */
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base->CTRL1 = regVal;
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}
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void XBARA_SetOutputSignalConfig(XBARA_Type *base,
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xbar_output_signal_t output,
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const xbara_control_config_t *controlConfig)
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{
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uint16_t regVal;
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/* Set active edge for edge detection, set interrupt or DMA function. */
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switch ((uint16_t)output)
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{
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#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_30
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case kXBARA1_OutputDmaChMuxReq30:
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#else
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case kXBARA_OutputDmamux18:
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#endif
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/* Assign regVal to CTRL0 register's value */
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regVal = (base->CTRL0);
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/* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN0, IEN0 */
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regVal &= (uint16_t)(
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~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK));
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/* Configure edge and request type */
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regVal |= (uint16_t)(XBARA_CTRL0_EDGE0(controlConfig->activeEdge) |
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((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT));
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/* Write regVal value into CTRL0 register */
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base->CTRL0 = regVal;
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break;
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#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_31
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case kXBARA1_OutputDmaChMuxReq31:
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#else
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case kXBARA_OutputDmamux19:
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#endif
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/* Assign regVal to CTRL0 register's value */
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regVal = (base->CTRL0);
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/* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN1, IEN1 */
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regVal &= (uint16_t)(
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~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK | XBARA_CTRL0_DEN1_MASK | XBARA_CTRL0_IEN1_MASK));
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/* Configure edge and request type */
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regVal |= (uint16_t)(XBARA_CTRL0_EDGE1(controlConfig->activeEdge) |
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((controlConfig->requestType) << XBARA_CTRL0_DEN1_SHIFT));
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/* Write regVal value into CTRL0 register */
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base->CTRL0 = regVal;
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break;
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#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_94
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case kXBARA1_OutputDmaChMuxReq94:
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#else
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case kXBARA_OutputDmamux20:
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#endif
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/* Assign regVal to CTRL1 register's value */
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regVal = (base->CTRL1);
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/* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN2, IEN2 */
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regVal &= (uint16_t)(
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~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN2_MASK | XBARA_CTRL1_IEN2_MASK));
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/* Configure edge and request type */
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regVal |= (uint16_t)(XBARA_CTRL1_EDGE2(controlConfig->activeEdge) |
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((controlConfig->requestType) << XBARA_CTRL1_DEN2_SHIFT));
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/* Write regVal value into CTRL1 register */
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base->CTRL1 = regVal;
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break;
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#if defined(FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95) && FSL_FEATURE_XBARA_OUTPUT_DMA_CH_MUX_REQ_95
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case kXBARA1_OutputDmaChMuxReq95:
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#else
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case kXBARA_OutputDmamux21:
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#endif
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/* Assign regVal to CTRL1 register's value */
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regVal = (base->CTRL1);
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/* Perform this command to avoid writing 1 into interrupt flag bits and clears bit DEN3, IEN3 */
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regVal &= (uint16_t)(
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~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK | XBARA_CTRL1_DEN3_MASK | XBARA_CTRL1_IEN3_MASK));
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/* Configure edge and request type */
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regVal |= (uint16_t)(XBARA_CTRL1_EDGE3(controlConfig->activeEdge) |
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((controlConfig->requestType) << XBARA_CTRL1_DEN3_SHIFT));
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/* Write regVal value into CTRL1 register */
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base->CTRL1 = regVal;
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break;
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default:
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break;
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}
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}
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