rt-thread/libcpu/arm/arm926/cpuport.c

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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
* SPDX-License-Identifier: Apache-2.0
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*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety modified from mini2440
* 2015-04-15 ArdaFu Add code for IAR
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*/
#include <rthw.h>
#include <rtthread.h>
#define ICACHE_MASK (rt_uint32_t)(1 << 12)
#define DCACHE_MASK (rt_uint32_t)(1 << 2)
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extern void machine_reset(void);
extern void machine_shutdown(void);
#if defined(__GNUC__) || defined(__ICCARM__)
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rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
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__asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r"(i));
return i;
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}
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm volatile(\
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"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
: "r"(bit) \
: "memory");
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}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm volatile(\
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"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
: "r"(bit) \
: "memory");
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}
#endif
#if defined(__CC_ARM)
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rt_inline rt_uint32_t cp15_rd(void)
{
rt_uint32_t i;
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__asm volatile
{
mrc p15, 0, i, c1, c0, 0
}
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return i;
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}
rt_inline void cache_enable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
orr value, value, bit
mcr p15, 0, value, c1, c0, 0
}
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}
rt_inline void cache_disable(rt_uint32_t bit)
{
rt_uint32_t value;
__asm volatile
{
mrc p15, 0, value, c1, c0, 0
bic value, value, bit
mcr p15, 0, value, c1, c0, 0
}
}
#endif
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/**
* enable I-Cache
*
*/
void rt_hw_cpu_icache_enable()
{
cache_enable(ICACHE_MASK);
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}
/**
* disable I-Cache
*
*/
void rt_hw_cpu_icache_disable()
{
cache_disable(ICACHE_MASK);
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}
/**
* return the status of I-Cache
*
*/
rt_base_t rt_hw_cpu_icache_status()
{
return (cp15_rd() & ICACHE_MASK);
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}
/**
* enable D-Cache
*
*/
void rt_hw_cpu_dcache_enable()
{
cache_enable(DCACHE_MASK);
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}
/**
* disable D-Cache
*
*/
void rt_hw_cpu_dcache_disable()
{
cache_disable(DCACHE_MASK);
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}
/**
* return the status of D-Cache
*
*/
rt_base_t rt_hw_cpu_dcache_status()
{
return (cp15_rd() & DCACHE_MASK);
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}
/**
* reset cpu by dog's time-out
*
*/
rt_weak void rt_hw_cpu_reset()
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{
rt_kprintf("Restarting system...\n");
machine_reset();
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while (1); /* loop forever and wait for reset to happen */
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/* NEVER REACHED */
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}
/**
* shutdown CPU
*
*/
rt_weak void rt_hw_cpu_shutdown()
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{
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rt_base_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
machine_shutdown();
while (level)
{
RT_ASSERT(0);
}
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}
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#ifdef RT_USING_CPU_FFS
/**
* This function finds the first bit set (beginning with the least significant bit)
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* in value and return the index of that bit.
*
* Bits are numbered starting at 1 (the least significant bit). A return value of
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* zero from any of these functions means that the argument was zero.
*
* @return return the index of the first bit set. If value is 0, then this function
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* shall return 0.
*/
#if defined(__CC_ARM)
int __rt_ffs(int value)
{
register rt_uint32_t x;
if (value == 0)
return value;
__asm
{
rsb x, value, #0
and x, x, value
clz x, x
rsb x, x, #32
}
return x;
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}
#elif defined(__GNUC__) || defined(__ICCARM__)
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int __rt_ffs(int value)
{
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return __builtin_ffs(value);
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}
#endif
#endif
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/*@}*/